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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com ? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer june 2003 rev. 1.0.0 general description the XRT75L03D is a three-channel fully integrated line interface unit (liu) with jitter attenuator for e3/ ds3/sts-1 applications. it incorporates 3 independent receivers, transmitters and jitter attenuators in a single 128 pin lqfp package. each channel of the XRT75L03D can be independently configured to operate in the data rate, e3 (34.368 mhz), ds3 (44.736 mhz) or sts-1 (51.84 mhz). each transmitter can be turned off and tri- stated for redundancy support or for conserving power. the XRT75L03Ds differential receiver provides high noise interference margin and is able to receive the data over 1000 feet of cable or with up to 12 db of cable attenuation. the XRT75L03D incorporates an advanced crystal- less jitter attenuator per channel that can be selected either in the transmit or receive path. the jitter attenuator performance meets the etsi tbr-24 and bellcore gr-499 specifications. the XRT75L03D provides both serial microprocessor interface as well as hardware mode for programming and control. the XRT75L03D supports local, remote and digital loop-backs. the device also has a built-in pseudo random binary sequence (prbs) generator and detector with the ability to insert and detect single bit error for diagnostic purposes. features receiver: on chip clock and data recovery circuit for high input jitter tolerance meets e3/ds3/sts-1 jitter tolerance requirement detects and clears los as per g.775 receiver monitor mode handles up to 20 db flat loss with 6 db cable attenuation on chip b3zs/hdb3 encoder and decoder that can be either enabled or disabled on-chip clock synthesizer provides the appropriate rate clock from a single 12.288 mhz clock provides low jitter output clock transmitter: compliant with bellcore gr-499, gr-253 and ansi t1.102 specification for transmit pulse tri-state transmit output capability for redundancy applications each transmitter can be turned on or off transmitters provide current drive output jitter attenuator: on chip advanced crystal-less jitter attenuator for each channel jitter attenuator can be selected in receive or transmit paths meets etsi tbr 24 jitter transfer requirements compliant with jitter transfer template outlined in itu g.751, g.752, g.755 and gr-499-core,1995 standards jitter attenuator can be disabled control and diagnostics: 5 wire serial microprocessor interface for control and configuration supports optional internal transmit driver monitoring hardware mode for control and configuration each channel supports local, remote and digital loop-backs single 3.3 v 5% power supply 5 v tolerant i/o available in 128 pin thermally enhanced lqfp package - 40c to 85c industrial temperature range applications e3/ds3 access equipment sts1-spe to ds3 de-synchronizing dslams digital cross connect systems csu/dsu equipment routers fiber optic terminals
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 2 transmit interface characteristics accepts either single-rail or dual-rail data from terminal equipment and generates a bipolar signal to the line integrated pulse shaping circuit built-in b3zs/hdb3 encoder (which can be disabled) accepts transmit clock with duty cycle of 30%-70% generates pulses that comply with the itu-t g.703 pulse template for e3 applications generates pulses that comply with the dsx-3 pulse template, as specified in bellcore gr-499 -core and ansi t1.102_1993 generates pulses that comply with the stsx-1 pulse template, as specified in bellcore gr-253-core transmitter can be turned off in order to support redundancy designs receive interface characteristics integrated adaptive receive equalization (optional) for optimal clock and data recovery declares and clears the los defect per itu-t g.775 requirements for e3 and ds3 applications meets jitter tolerance requirements, as specified in itu-t g.823_1993 for e3 applications meets jitter tolerance requirements, as specified in bellcore gr-499-core for ds3 applications declares loss of signal (los) and loss of lock (lol) alarms built-in b3zs/hdb3 decoder (which can be disabled) recovered data can be muted while the los condition is declared outputs either single-rail or dual-rail data to the terminal equipment f igure 1. b lock d iagram of the xrt 75l03d host/hw sts-1/ds3_(n) e3_(n) reqen_(n) rtip_(n) rring_(n) sr/dr XRT75L03D rlb_(n) rlos_(n) jatx/rx tpdata_(n) tndata_(n) txclk_(n) taos_(n) txlev_(n) txon_(n) channel 2 channel 0 channel 1 notes: 1. (n) = 0, 1 or 2 for respective channels 2. serial processor interface input pins are shared by the three channels in "host" mode and redefined in the "hard ware" mode. device monitor mtip_(n) mring_(n) dmo_(n) timing control ttip_(n) tring_(n) tx pulse shaping hdb3/ b3zs encoder rlol_(n) rxon rxclkinv rxclk_(n) rpos_(n) rneg_(n)/ lcv_(n) tx control jitter attenuator mux line driver losthr llb_(n) invert remote loopback hdb3/ b3zs decoder mux agc/ equalizer peak detector los detector slicer jitter attenuator serial processor interface local loopback clock & data recovery clock synthesizer e3clk,ds3clk, sts-1clk reset cs sclk int sdo sdi clkout
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 3 f igure 2. p in o ut of the XRT75L03D ordering information p art n umber p ackage o perating t emperature r ange XRT75L03Div 128 pin lqfp - 40 c to + 85 c rlol_2 rlos_2 ict rlol_0 rlos_0 rxdgnd_0 rpos_0 rneg_0/lcv_0 rxclk_0 rxdvdd_0 rxdvdd_2 rpos_2 rneg_2/lcv_2 rxclk_2 rxdgnd_2 agnd_0 jagnd_2 jagnd_0 javdd_0 javdd_2 ja0 jatx/rx ja1 txagnd_0 dmo_0 txavdd_0 txon_1 tndata_1 tpdata_1 txclk_1 mring_1 mtip_1 taos_1 taos_2 txlev_1 txlev_2 ttip_1 txvdd_1 tring_1 txgnd_1 txagnd_2 mring_2 mtip_2 txgnd_2 tring_2 txvdd_2 ttip_2 dmo_2 txavdd_2 tndata_2 tpdata_2 txclk_2 txgnd_0 tring_0 txvdd_0 ttip_0 mtip_0 mring_0 tndata_0 tpdata_0 txclk_0 txlev_0 taos_0 txon_0 rlol_1 rlos_1 exdgnd sfm_en e3clk/clk_en ds3clk/clk_out sts-1clk/12m exdvdd rxdvdd_1 rpos_1 rneg_1/lcv_1 rxclk_1 rxdgnd_1 agnd_1 jadgnd jagnd_1 jadvdd javdd_1 refavdd rxa rxb refgnd txon_2 txagnd_1 dmo_1 txavdd_1 XRT75L03D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 test reset agnd_2 losthr sts-1/ds3_1 llb_1 rlb_1 reqen_1 e3_1 rxavdd_1 rring_1 rtip_1 rxagnd_1 rxagnd_2 rtip_2 rring_2 rxavdd_2 e3_2 reqen_2 rlb_2 llb_2 sts-1/ds3_2 rxagnd_0 rtip_0 rring_0 rxavdd_0 e3_0 reqen_0 rlb_0 llb_0 sts-1/ds3_0 losmut/int host/hw rxmon/sdo rxon/sdi txclkinv/sclk rxclkinv/cs sr/dr
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer i general description ............................................................................................... 1 f eatures .............................................................................................................................. ...................... 1 a pplications .............................................................................................................................. ................ 1 t ransmit i nterface c haracteristics ...................................................................................................... 2 r eceive i nterface c haracteristics ........................................................................................................ 2 figure 1. block diagram of the xrt 75l03d ..................................................................................... ............... 2 figure 2. pin out of the XRT75L03D ............................................................................................ .................... 3 ordering information .......................................................................................................... ......... 3 pin descriptions (by function) ............................................................................. 4 s ystem -s ide t ransmit i nput and t ransmit c ontrol p ins ...................................................................... 4 t ransmit l ine s ide p ins ............................................................................................................................ 8 s ystem -s ide r eceive o utput and r eceive c ontrol p ins .................................................................... 10 r eceive l ine s ide p ins ............................................................................................................................ 1 7 c lock i nterface .............................................................................................................................. ........ 18 g eneral c ontrol p ins ........................................................................................................................... 19 c ontrol and a larm i nterface ............................................................................................................... 21 j itter a ttenuator interface ................................................................................................................. 21 p ower s upply and g round p ins ............................................................................................................ 24 XRT75L03D p in l isting in n umerical o rder ......................................................................................... 26 1.0 electrical characteristics ................................................................................................ . 31 t able 1: a bsolute m aximum r atings ............................................................................................................ 31 t able 2: dc e lectrical c haracteristics : ................................................................................................... 31 2.0 timing characteristics .................................................................................................... ........ 32 figure 3. typical interface between terminal equipment and the XRT75L03D (dual-rail data) ....................... 32 figure 4. transmitter terminal input timing ................................................................................... ................ 32 figure 5. receiver data output and code violation timing ...................................................................... ........ 33 figure 6. transmit pulse amplitude test circuit for e3, ds3 and sts-1 rates ............................................... 33 3.0 line side characteristics: ................................................................................................ ..... 34 3.1 e3 line side parameters : ............................................................................................................................. 34 figure 7. pulse mask for e3 (34.368 mbits/s) interface as per itu-t g.703 ..................................................... 34 t able 3: e3 t ransmitter line side output and receiver line side input specifications ........................... 35 figure 8. bellcore gr-253 core transmit output pulse template for sonet sts-1 applications ............ 36 t able 4: sts-1 p ulse m ask e quations ........................................................................................................ 36 t able 5: sts-1 t ransmitter l ine s ide o utput and r eceiver l ine s ide i nput s pecifications (gr-253) . 37 figure 9. transmit ouput pulse template for ds3 as per bellcore gr-499 .................................................. 38 t able 6: ds3 p ulse m ask e quations ........................................................................................................... 38 t able 7: ds3 t ransmitter l ine s ide o utput and r eceiver l ine s ide i nput s pecifications (gr-499) ..... 39 figure 10. microprocessor serial interface structure .......................................................................... ............ 39 figure 11. timing diagram for the microprocessor serial interface ............................................................. ... 40 t able 8: m icroprocessor s erial i nterface t imings ( ta = 250c, vdd=3.3v 5% and load = 10 p f) ..... 40 functional description: ........................................................................................ 41 4.0 the transmitter section: .................................................................................................. ............... 41 figure 12. single-rail or nrz data format (encoder and decoder are enabled) ......................................... 41 figure 13. dual-rail data format (encoder and decoder are disabled) ......................................................... 4 1 4.1 t ransmit c lock : ............................................................................................................................. .............. 42 4.2 b3zs/hdb3 e ncoder : ............................................................................................................................. ..... 42 4.2.1 b3zs encoding: .......................................................................................................... ....................... 42 4.2.2 hdb3 encoding: .......................................................................................................... ....................... 42 figure 14. b3zs encoding format ............................................................................................... .................. 42 figure 15. hdb3 encoding format ............................................................................................... .................. 42 4.3 t ransmit p ulse s haper : ............................................................................................................................. . 43 4.3.1 guidelines for using transmit build out circuit: ........................................................................ .... 43 4.3.2 interfacing to the line: ................................................................................................ ........................ 43 4.4 t ransmit d rive m onitor : ............................................................................................................................. 44 4.5 t ransmitter s ection o n /o ff : ...................................................................................................................... 44 5.0 the receiver section: ..................................................................................................... ................. 44
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XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 ii 5.1 agc/e qualizer : ............................................................................................................................. ............... 44 figure 16. transmit driver monitor set-up. .................................................................................... ................. 44 5.1.1 interference tolerance: ................................................................................................. .................... 45 figure 17. interference margin test set up for ds3/sts-1 ...................................................................... ..... 45 5.2 c lock and d ata r ecovery : ......................................................................................................................... 46 figure 18. interference margin test set up for e3. ............................................................................ ............ 46 t able 9: i nterference m argin t est r esults .............................................................................................. 46 5.3 b3zs/hdb3 d ecoder : ............................................................................................................................. ..... 47 5.4 los (l oss of s ignal ) d etector : ................................................................................................................ 47 5.4.1 ds3/sts-1 los condition: ................................................................................................ ................ 47 d isabling alos/dlos d etection : ......................................................................................................... 47 5.4.2 e3 los condition: ....................................................................................................... ...................... 47 t able 10: t he alos (a nalog los) d eclaration and c learance t hresholds for a given setting of losthr and reqen (ds3 and sts-1 a pplications ) ................................................................... 47 figure 19. loss of signal definition for e3 as per itu-t g.775 ................................................................ .... 48 figure 20. loss of signal definition for e3 as per itu-t g.775. ............................................................... ..... 48 5.4.3 muting the recovered data with los condition: ........................................................................... . 49 6.0 jitter: ................................................................................................................... .............................. 49 6.1 j itter t olerance - r eceiver : ...................................................................................................................... 49 6.1.1 ds3/sts-1 jitter tolerance requirements: ................................................................................ ..... 49 figure 21. jitter tolerance measurements ...................................................................................... ............... 49 6.1.2 e3 jitter tolerance requirements: ....................................................................................... ............ 50 figure 22. input jitter tolerance for ds3/sts-1 .............................................................................. ............ 50 figure 23. input jitter tolerance for e3 ..................................................................................... .................... 50 6.2 j itter t ransfer - r eceiver /t ransmitter : .................................................................................................. 51 6.3 j itter a ttenuator : ............................................................................................................................. ......... 51 t able 11: j itter a mplitude versus m odulation f requency (j itter t olerance ) ..................................... 51 t able 12: j itter t ransfer s pecification /r eferences ............................................................................... 51 6.3.1 jitter generation: ...................................................................................................... ......................... 52 7.0 serial host interface: .................................................................................................... ................... 52 t able 13: j itter t ransfer p ass m asks ....................................................................................................... 52 figure 24. jitter transfer requirements and jitter attenuator performance .................................................. 52 t able 14: f unctions of shared pins ............................................................................................................ 53 t able 15: XRT75L03D r egister m ap - q uick l ook ..................................................................................... 54 .............................................................................................................................. ................................... 56 the register map and description for the XRT75L03D 3-channel ds3/e3/sts-1 liu ic .. 56 legend: ........................................................................................................................ ..........................................56 t able 16: c ommand r egister a ddress m ap , within the XRT75L03D 3-c hannel ds3/e3/sts-1 liu w / j itter a ttenuator ic ........................................................................................................................... ...... 56 the global/chip-level registers ............................................................................................... 58 .............................................................................................................................. ................................... 58 register description - global registers .............................................................................. 58 t able 17: l ist and a ddress l ocations of g lobal r egisters .................................................................... 58 t able 18: aps/r edundancy c ontrol r egister - cr0 (a ddress l ocation = 0 x 00) .................................. 58 t able 19: b lock l evel i nterrupt e nable r egister - cr32 (a ddress l ocation = 0 x 20) ......................... 61 t able 20: b lock l evel i nterrupt s tatus r egister - cr33 (a ddress l ocation = 0 x 21) ......................... 62 t able 21: d evice /p art n umber r egister - cr62 (a ddress l ocation = 0 x 3e) .......................................... 63 .............................................................................................................................. ................................... 64 the per-channel registers ..................................................................................................... .... 64 t able 22: c hip r evision n umber r egister - cr63 (a ddress l ocation = 0 x 3f) ........................................ 64 t able 23: c ommand r egister a ddress m ap , within the XRT75L03D 3-c hannel ds3/e3/sts-1 liu w / j itter a ttenuator ic ........................................................................................................................... ...... 64 register description - per channel registers ................................................................... 66 t able 24: s ource l evel i nterrupt e nable r egister - c hannel 0 a ddress l ocation = 0 x 01 ................. 66 t able 25: s ource l evel i nterrupt s tatus r egister - c hannel 0 a ddress l ocation = 0 x 02 ................. 68
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer iii t able 26: a larm s tatus r egister - c hannel 0 a ddress l ocation = 0 x 03 ................................................ 70 t able 27: t ransmit c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 04 ......................................... 75 t able 28: r eceive c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 05 ........................................... 78 t able 29: c hannel c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 06 ......................................... 80 t able 30: j itter a ttenuator c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 07 ......................... 83 8.0 diagnostic features: ...................................................................................................... .................. 85 8.1 prbs g enerator and d etector : ................................................................................................................ 85 8.2 loopbacks: ................................................................................................................ ............................... 85 8.2.1 analog loopback: ........................................................................................................ ............... 85 figure 25. prbs mode .......................................................................................................... ....................... 85 figure 26. analog loopback .................................................................................................... ....................... 86 8.2.2 digital loopback: ....................................................................................................... ................. 87 8.2.3 remote loopback: ........................................................................................................ ............... 87 figure 27. digital loopback ................................................................................................... ......................... 87 figure 28. remote loopback .................................................................................................... ...................... 87 8.3 transmit all ones (taos): ................................................................................................. .................. 88 figure 29. transmit all ones (taos) ........................................................................................... .................. 88 9.0 the sonet/sdh de-sync function within the XRT75L03D ............................................... 89 9.1 background and detailed information - sonet de-sync applications .......................... 89 figure 30. a simple illustration of a ds3 signal being mapped into and transported over the sonet network 90 9.2 mapping/de-mapping jitter/wander .......................................................................................... ...... 91 9.2.1 how ds3 data is mapped into sonet ...................................................................................... 91 figure 31. a simple illustration of the sonet sts-1 frame ..................................................................... .... 92 figure 32. a simple illustration of the sts-1 frame structure with the toh and the envelope capacity bytes designated .................................................................................................................... ................ 93 figure 33. the byte-format of the toh within an sts-1 frame ................................................................... . 94 figure 34. the byte-format of the toh within an sts-1 frame ................................................................... . 95 figure 35. illustration of the byte structure of the sts-1 spe ................................................................ ....... 96 figure 36. an illustration of telcordia gr-253-core's recommendation on how map ds3 data into an sts-1 spe ........................................................................................................................... .................... 97 figure 37. a simplified "bit-oriented" version of telcordia gr-253-core's recommendation on how to map ds3 data into an sts-1 spe .................................................................................................... .... 97 9.2.2 ds3 frequency offsets and the use of the "stuff opportunity" bits ............................................ 98 figure 38. a simple illustration of a ds3 data-stream being mapped into an sts-1 spe, via a pte .......... 99 figure 39. an illustration of the sts-1 spe traffic that will be generated by the "source" pte, when mapping in a ds3 signal that has a bit rate of 44.736mbps + 1ppm, into an sts-1 signal .......................... 100 9.3 j itter /w ander due to p ointer a djustments .......................................................................................... 102 9.3.1 the concept of an sts-1 spe pointer ..................................................................................... ...... 102 figure 40. an illustration of the sts-1 spe traffic that will be generated by the source pte, when mapping a ds3 signal that has a bit rate of 44.736mbps - 1ppm, into an sts-1 signal .............................. 102 figure 41. an illustration of an sts-1 spe straddling across two consecutive sts-1 frames ..................... 103 9.3.2 pointer adjustments within the sonet network .......................................................................... 1 04 figure 42. the bit-format of the 16-bit word (consisting of the h1 and h2 bytes) with the 10 bits, reflecting the location of the j1 byte, designated ........................................................................................... .. 104 figure 43. the relationship between the contents of the "pointer bits" (e.g., the 10-bit expression within the h1 and h2 bytes) and the location of the j1 byte within the envelope capacity of an sts-1 frame ... 104 9.3.3 causes of pointer adjustments ........................................................................................... ........... 105 figure 44. an illustration of an sts-1 signal being processed via a slip buffer ........................................... 106 figure 45. an illustration of the bit format within the 16-bit word (consisting of the h1 and h2 bytes) with the "i" bits designated ............................................................................................................... ............. 107 figure 46. an illustration of the bit-format within the 16-bit word (consisting of the h1 and h2 bytes) with the "d" bits designated ........................................................................................................... ........... 108 9.3.4 why are we talking about pointer adjustments? .......................................................................... 109 9.4 c lock g apping j itter .............................................................................................................................. ... 109 figure 47. illustration of the typical applications for the XRT75L03D in a sonet de-sync application .... 109
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XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 iv 9.5 a r eview of the c ategory i i ntrinsic j itter r equirements ( per t elcordia gr-253-core) for ds3 ap - plications .............................................................................................................................. .......................................... 110 t able 31: s ummary of "c ategory i i ntrinsic j itter r equirement per t elcordia gr-253-core, for ds3 applications .............................................................................................................................. .... 110 9.5.1 ds3 de-mapping jitter ................................................................................................... .................. 111 9.5.2 single pointer adjustment ............................................................................................... ............... 111 figure 48. illustration of single pointer adjustment scenario ................................................................. ..... 111 9.5.3 pointer burst ........................................................................................................... ......................... 112 9.5.4 phase transients ........................................................................................................ ..................... 112 figure 49. illustration of burst of pointer adjustment scenario ............................................................... ..... 112 figure 50. illustration of "phase-transient" pointer adjustment scenario ................................................... 11 2 9.5.5 87-3 pattern ............................................................................................................ .......................... 113 9.5.6 87-3 add ................................................................................................................ ............................ 113 figure 51. an illustration of the 87-3 continuous pointer adjustment pattern ............................................. 113 9.5.7 87-3 cancel ............................................................................................................. .......................... 114 figure 52. illustration of the 87-3 add pointer adjustment pattern ............................................................ .. 114 figure 53. illustration of 87-3 cancel pointer adjustment scenario ............................................................ . 114 9.5.8 continuous pattern ...................................................................................................... .................... 115 9.5.9 continuous add ......................................................................................................... ..................... 115 figure 54. illustration of continuous periodic pointer adjustment scenario ............................................... 115 9.5.10 continuous cancel ...................................................................................................... .................. 116 figure 55. illustration of continuous-add pointer adjustment scenario ....................................................... 1 16 figure 56. illustration of continuous-cancel pointer adjustment scenario .................................................. 116 9.6 a r eview of the ds3 w ander r equirements per ansi t1.105.03 b -1997. ............................................. 117 9.7 a r eview of the i ntrinsic j itter and w ander c apabilities of the XRT75L03D in a typical system appli - cation .............................................................................................................................. .............................................. 117 9.7.1 intrinsic jitter test results ........................................................................................... ................... 117 t able 32: s ummary of "c ategory i i ntrinsic j itter t est r esults " for sonet/ds3 a pplications ..... 117 9.7.2 wander measurement test results ......................................................................................... ...... 118 9.8 d esigning with the XRT75L03D ................................................................................................................. 11 8 9.8.1 how to design and configure the XRT75L03D to permit a system to meet the above-mentioned intrinsic jitter and wander requirements ...................................................................................... ............................... 118 figure 57. illustration of the XRT75L03D being connected to a mapper ic for sonet de-sync applications .. 118 c hannel c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 06 ................................................. 119 c hannel 1 a ddress l ocation = 0 x 0e ......................................... 119 c hannel 2 a ddress l ocation = 0 x 16 ......................................... 119 c hannel c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 06 ................................................. 120 c hannel 1 a ddress l ocation = 0 x 0e .............................................. 120 c hannel 2 a ddress l ocation = 0 x 16 ............................................... 120 j itter a ttenuator c ontrol r egister - (c hannel 0 a ddress l ocation = 0 x 07 ............................... 120 c hannel 1 a ddress l ocation = 0 x 0f .................................. 120 c hannel 2 a ddress l ocation = 0 x 17 .................................. 120 9.8.2 recommendations on pre-processing the gapped clocks (from the mapper/asic device) prior to routing this ds3 clock and data-signals to the transmit inputs of the XRT75L03D .............................................. 121 j itter a ttenuator c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 07 ................................ 121 c hannel 1 a ddress l ocation = 0 x 0f ............................ 121 c hannel 2 a ddress l ocation = 0 x 17 ............................ 121 j itter a ttenuator c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 07 ................................ 121 c hannel 1 a ddress l ocation = 0 x 0f ........................... 121 c hannel 2 a ddress l ocation = 0 x 17 ........................... 121 figure 58. illustration of minor pattern p1 ................................................................................... ......... 122 figure 59. illustration of minor pattern p2 ................................................................................... ......... 123 figure 60. illustration of procedure which is used to synthesize major pattern a .............................. 123 figure 61. illustration of minor pattern p3 ................................................................................... ......... 124 figure 62. illustration of procedure which is used to synthesize pattern b ........................................... 124 figure 63. illustration of the super pattern which is output via the "oc-n to ds3" mapper ic ............ 125
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer v figure 64. simple illustration of the XRT75L03D being used in a sonet de-synchronizer" application ... 125 9.8.3 how does the XRT75L03D permit the user to comply with the sonet aps recovery time require- ments of 50ms (per telcordia gr-253-core)? .................................................................................... ....................... 126 t able 33: m easured aps r ecovery t ime as a function of ds3 ppm offset .......................................... 126 9.8.4 how should one configure the XRT75L03D, if one needs to support "daisy-chain" testing at the end customer's site? .......................................................................................................... ........................................... 127 j itter a ttenuator c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 07 ................................. 127 c hannel 1 a ddress l ocation = 0 x 0f ............................ 127 c hannel 2 a ddress l ocation = 0 x 17 ............................ 127 j itter a ttenuator c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 07 ................................. 127 c hannel 1 a ddress l ocation = 0 x 0f ................................... 127 c hannel 2 a ddress l ocation = 0 x 17 ................................... 127 ordering information .......................................................................................................... ..... 128 p ackage d imensions - 14 x 20 mm , 128 pin package .............................................................................. 128 r evisions .............................................................................................................................. ................. 129
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 4 pin descriptions ( by function ) system-side transmit input and transmit control pins p in #s ignal n ame t ype d escription 38 1 125 txon_0 txon_1 txon_2 i transmitter on input - channel 0: transmitter on input - channel 1: transmitter on input - channel 2: these input pins are used to either enable or disable the transmit output driver corresponding to channel_n. "low" - disables the transmit output driver of the corresponding channel. in this setting, the corresponding ttip_n and tring_n output pins will be tri-stated. "high" - enables the transmit output driver of the corresponding channel. in this setting, the corresponding ttip_n and tring_n output pins will be enabled. n otes : 1. even when the XRT75L03D is configured in host mode, these pins will be active. to enable software control of the transmit output driver outputs, pull these pins "high". 2. when transmitters are turned off either in host or hardware mode, the ttip and tring outputs are tri-stated. 3. these pins are internally pulled "high" 35 4 26 txclk_0 txclk_1 txclk_2 i transmit clock input - channel 0: transmit clock input f - channel 1: transmit clock input - channel 2: these input pins have two functions: ? they function as the timing source for the transmit section of the corresponding channel within the XRT75L03D. ? they also are used by the transmit section of the liu ic to sample the corresponding tpdata_n and tndata_n input pin. n ote : the user is expected to supply a 44.736mhz 20ppm clock signal (for ds3 applications), 34.368mhz 20 ppm clock signal (for e3 applications) or a 51.84mhz 4.6ppm clock signal (for sts-1, stratum 3e or better applications).
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 5 34 3 25 tpdata_0/txdata_0 tpdata_1/txdata_1 tpdata_2/txdata_2 i transmit positive data input - channel 0 : transmit positive data input - channel 1 : transmit positive data input - channel 2 : transmit positive data/data input - channel n: the function of these input pins depends upon whether the corresponding channel has been configured to operate in the single-rail or dual-rail mode. single rail mode - transmit data input - channel n: if the channel has been configured to operate in the single-rail mode, then all transmit output data will be serially applied to this input pin. this signal will latched into the transmit section circuitry upon either the rising or fall- ing edge of the txclk_n signal, depending upon user configuration. in the single-rail mode, the transmit section of the liu ic will then encode this data into either the b3zs line code (for ds3 and sts-1 applications) or the hdb3 line code (for e3 applications). dual rail mode - transmit positive data input - channel n: if the channel has been configured to operate in the dual-rail mode, then the user should apply a pulse to this input pin, anytime the transmit section of the liu ic is suppose to generate and transmit a positive-polarity pulse onto the line. this signal will be latched into the transmit section circuitry upon either the rising or falling edge of the txclk_n signal, depending upon user configuration. in the dual-rail mode, the transmit section of the liu ic will not encode this data into either the b3zs or hdb3 line codes. if the user configures the liu ic to operate in the dual-rail mode, then b3zs/hdb3 encoding must have already been done prior to providing the transmit output data to this input pin. 33 2 24 tndata_0 tndata_1 tndata_2 i transmit negative data input - channel 0: transmit negative data input - channel 1: transmit negative data input - channel 2: if a channel has been configured to operate in the dual-rail mode, then the user should apply a pulse to this input pin anytime the transmit section of the liu ic is suppose to generate and transmit a negative-polarity pulse onto the line. this signal will be latched into the transmit section circuitry upon either the rising or falling edge of the txclk_n signal, depending upon user configuration. n ote : if the channel has been configured operate in the single-rail mode, then this input pin has no function, and should be tied to gnd. system-side transmit input and transmit control pins p in #s ignal n ame t ype d escription
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 6 37 7 8 ta o s _ 0 ta o s _ 1 ta o s _ 2 i transmit "all ones" input - channel 0: transmit "all ones" input - channel 1: transmit "all ones" input - channel 2: these input pin are used to configure the transmit section of the corre- sponding channel to generate and transmit an unframed "all ones" pattern via the ds3, e3 or sts-1 line signal to the remote terminal equipment. when this configuration is implemented the transmit section will ignore the data that it is accepting from the system-side equipment and will overwrite this data will the "all ones" pattern. "low" - does not configure the channel to transmit an unframed "all ones" pattern to the remote terminal equipment. in this mode, the transmit sec- tion of the channel will output data based upon the signals that are applied to the txpos_n and txneg_n input pins. "high" - configures the channel to transmit an unframed "all ones" pattern to the remote terminal equipment. in this mode, the transmit section will override the data that is applied to the txpos_n and txneg_n input pins, and will proceed to generate and transmit an unframed "all ones" pattern. 4. this input pin is ignored if the XRT75L03D is operating in the host mode and should be tied to gnd. 5. these input pins are internally pulled down. 36 9 10 txlev_0 txlev_1 txlev_2 i transmit line build-out enable/disable select - channel 0: transmit line build-out enable/disable select - channel 1: transmit line build-out enable/disable select - channel 2: these input pins are used to enable or disable the transmit line build-out (e.g., pulse-shaping) circuit within the corresponding channel. the user should set these input pins either "high" or "low" based upon the following guidelines. "low" - if the cable length between the transmit output of the correspond- ing channel and the dsx-3/stsx-1 location is 225 feet or less. "high" - if the cable length between the transmit output of the correspond- ing channel and the dsx-3/stsx-1 location is 225 feet or more. n otes : 1. these guidelines must be followed in order to insure that the transmit section of channel_n will always generate a ds3 pulse that complies with the isolated pulse template requirements per bellcore gr-499-core, or an sts-1 pulse that complies with the pulse template requirements per telcordia gr-253-core. 2. this input pin is inactive if the XRT75L03D has been configured to operate in the host mode, or if the corresponding channel has been configured to operate in the e3 mode. if either of these cases are true, then tie this input pin to gnd. 3. these input pins are internally pulled "low". system-side transmit input and transmit control pins p in #s ignal n ame t ype d escription
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 7 40 127 22 dmo_0 dmo_1 dmo_2 o drive monitor output - channel 0: drive monitor output - channel 1: drive monitor output - channel 2: these output signals are used to indicate some sort of fault condition within the transmit output signal path. this output pin will toggle "high" anytime the transmit drive monitor cir- cuitry either, via the corresponding mtip and mring input pins or inter- nally, detects no bipolar pulses via the transmit output line signal (e.g., via the ttip_n and tring_n output pins) for 128 bit-periods. this output pin will be driven "low" anytime the transmit drive monitor cir- cuitry has detected at least one bipolar pulse via the transmit output line signal within the last 128 bit periods. 67 txclkinv/ sclk i hardware mode: transmit clock invert host mode: serial clock input: hardware mode this input pin is used to select the edge of the txclk_n input that the transmit section of all channels will use to sample the tpdata_n and tndata_n input pins. setting this input pin high configures all three transmitters to sample the tpdata_n and tndata_n data on the rising edge of the txclk_n . setting this input pin low configures all three transmitters to sample the tpdata_n and tndata_n data on the falling edge of the txclk_n . host mode in the host mode this pin functions as sclk input pin please refer to the pin descriptions for the microprocessor interface. system-side transmit input and transmit control pins p in #s ignal n ame t ype d escription
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 8 transmit line side pins p in #s ignal n ame t ype d escription 30 11 21 ttip_0 ttip_1 ttip_2 o transmit ttip output - positive polarity signal - channel 0: transmit ttip output - positive polarity signal - channel 1: transmit ttip output - positive polarity signal - channel 2: these output pins along with the corresponding tring_n output pins, function as the transmit ds3/e3/sts-1 line output signal drivers for a given channel, of the XRT75L03D. connect this signal and the corresponding tring_n output signal to a 1:1 transformer. whenever the transmit section of the channel generates and transmits a posi- tive-polarity pulse onto the line, this output pin will be pulsed to a "higher-volt- age" than its corresponding tring_n output pins. conversely, whenever the transmit section of the channel generates and trans- mit a negative-polarity pulse onto the line, this output pin will be pulsed to a "lower-voltage" than its corresponding tring_n output pin. n ote : this output pin will be tri-stated whenever the corresponding txon_n input pin or bit-field is set to "0". 28 13 19 tring_0 tring_1 tring_2 o transmit ring output - negative polarity signal - channel 0: transmit ring output - negative polarity signal - channel 1: transmit ring output - negative polarity signal - channel 2: these output pins along with the corresponding ttip_n output pins, function as the transmit ds3/e3/sts-1 line output signal drivers for a given channel, within the XRT75L03D. connect this signal and the corresponding ttip_n output signal to a 1:1 trans- former. whenever the transmit section of the channel generates and transmits a posi- tive-polarity pulse onto the line. this output pin will be pulsed to a "lower-volt- age" than its corresponding ttip_n output pins. conversely, whenever the transmit section of the channel generates and trans- mit a negative-polarity pulse onto the line. this output pin will be pulsed to a "higher-voltage" than its corresponding ttip_n output pin. n ote : this output pin will be tri-stated whenever the corresponding txon_n input pin or bit-field is set to "0".
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 9 31 6 17 mtip_0 mtip_1 mtip_2 i monitor tip input - positive polarity signal - channel 0: monitor tip input - positive polarity signal - channel 1: monitor tip input - positive polarity signal - channel 2: these input pins along with mring_n function as the transmit drive monitor output (dmo) input monitoring pins. to (1) monitor the transmit output line signal and (2) to perform this monitoring externally, then this pin must be con- nected to the corresponding ttip_n output pin via a 274 ohm series resistor. similarly, the mring_n input pin must also be connected to its corresponding tring_n output pin via a 274 ohm series resistor. the mtip_n and mring_n input pins will continuously monitor the transmit output line signal via the ttip_n and tring_n output pins for bipolar activity. if these pins do not detect any bipolar activity for 128 bit periods, then the trans- mit drive monitor circuit will drive the corresponding dmo_n output pin "high" in order to denote a possible fault condition in the transmit output line signal path. n otes : 1. these input pins are inactive if the user choose to internally monitor the transmit output line signal. 2. internal monitoring is only available as an option if the XRT75L03D in is being operated in the host mode. 32 5 16 mring_0 mring_1 mring_2 i monitor ring input - channel 0: monitor ring input - channel 1: monitor ring input - channel 2: these input pins along with mtip_n function as the transmit drive monitor out- put (dmo) input monitoring pins. to (1) monitor the transmit output line signal and (2) to perform this monitoring externally, then this input pin must be con- nected to the corresponding tring_n output pin via a 274 ohm series resistor. similarly, the mtip_n input pin must be connected to its corresponding ttip_n output pin via a 274 ohm series resistor. the mtip_n and mring_n input pins will continuously monitor the transmit output line signal via the ttip_n and tring_n output pins for bipolar activity. if these pins do not detect any bipolar activity for 128 bit periods, then the trans- mit drive monitor circuit will drive the corresponding dmo_n output pin "high" to indicate a possible fault condition in the transmit output line signal path. n otes : 1. these input pins are inactive if the user chooses to internally monitor the transmit output line signal. 2. internal monitoring is only available as an option if the XRT75L03D is being operated in the host mode. transmit line side pins p in #s ignal n ame t ype d escription
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 10 system-side receive output and receive control pins p in #s ignal n ame t ype d escription 60 104 63 rlos_0 rlos_1 rlos_2 o receive loss of signal output indicator - channel 0: receive loss of signal output indicator - channel 1: receive loss of signal output indicator - channel 2: this output pin indicates whether or not the corresponding channel is declaring the loss of signal (los) defect condition. "low" - indicates that the corresponding channel is not currently declaring the los defect condition. "high" - indicates that the corresponding channel is currently declaring the los defect condition. 61 103 64 rlol_0 rlol_1 rlol_2 o receive loss of lock output indicator - channel 0: receive loss of lock output indicator - channel 1: receive loss of lock output indicator - channel 2: this output pin indicates whether or not the corresponding channel is declaring the loss of lock (lol) condition. "low" - indicates that the corresponding channel is not declaring the lol con- dition. "high" - indicates that the corresponding channel is currently declaring the lol condition. n ote : the receive section of a given channel will declare the lol condition anytime the frequency of the recovered clock (rclk) signal differs from that of the e3clk input clock signal (if the channel is operating in the e3 mode), the ds3clk input clock signal (if the channel is operating in the ds3 mode) the sts-1clk input clock signal (if the channel is operating in the sts-1 mode), or that clock signal which is derived from the sfm clock synthesizer block (if the chip is operating in the single-frequency mode) by 0.5% (or 5000ppm) or more. 58 112 53 rpos_0/rdata_0 rpos_1/rdata_1 rpos_2/rdata_2 o receive positive data output - receive data output - channel 0: receive positive data output - receive data output - channel 1: receive positive data output - receive data output - channel 2: the function of these output pins depends upon whether the channel/device has been configured to operate in the single-rail or dual-rail mode. dual-rail mode - receive positive polarity data output if the channel/device has been configured to operate in the dual-rail mode, then all positive-polarity data will be output via this output pin. the negative- polarity data will be output via the corresponding rneg_n output pin. in other words, the receive section of the corresponding channel will pulse this output pin "high" for one period of rclk_n anytime it receives a positive-polarity pulse via the rtip/rring input pins. the data that is output via this pin is updated upon a user-selectable edge of the rclk_n output clock signal. single-rail mode - receive data output if the channel/device has been configured to operate in the single-rail mode, then all receive (or recovered) data will be output via this output pin. the data that is output via this pin is updated upon a user-selectable edge of the rclk_n output clock signal.
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 11 57 113 52 rneg_0/lcv_0 rneg_1/lcv_1 rneg_2/lcv_2 o receive negative data output/line code violation indicator - channel 0: receive negative data output/line code violation indicator - channel 1: receive negative data output/line code violation indicator - channel 2: the function of these pins depends on whether the XRT75L03D is configured in single rail or dual rail mode. dual-rail mode - receive negative polarity data output if the channel/device has been configured to operate in the dual-rail mode, then all negative-polarity data will be output via this output pin. the positive- polarity data will be output via the corresponding rpos_n output pin. in other words, the receive section of the corresponding channel will pulse this output pin "high" for one period of rclk_n anytime it receives a negative-polarity pulse via the rtip/rring input pins. the data that is output via this pin is updated upon a user-selectable edge of the rclk_n output clock signal. single-rail mode - line code violation indicator output if the channel/device has been configured to operate in the single-rail mode, then this particular output pin will function as the line code violation indicator output. in this configuration, the receive section of the channel will pulse this output pin "high" for at least one rclk period whenever it detects either an lcv (line code violation) or an exz (excessive zero event). the data that is output via this pin is updated upon a user-selectable edge of the rclk_n output clock signal. 56 114 51 rxclk_0 rxclk_1 rxclk_2 o receive clock output - channel 0: receive clock output - channel 1: receive clock output - channel 2: this output pin functions as the receive or recovered clock signal. all receive (or recovered) data will output via the rpos_n and rneg_n outputs upon the user-selectable edge of this clock signal. additionally, if the device/channel has been configured to operate in the single- rail mode, then the rneg_n/lcv_n output pins will also be updated upon the user-selectable edge of this clock signal. 75 95 84 reqen_0 reqen_1 reqen_2 i receive equalization enable input - channel 0: receive equalization enable input - channel 1: receive equalization enable input - channel 2: these input pins are used to either enable or disable the receive equalizer block within the receive section of the corresponding channel. "low" - disables the receive equalizer within the corresponding channel. "high" - enables the receive equalizer within the corresponding channel. n otes : 1. for virtually all applications, it is recommend that this input pin be pulled "high" and enable the receive equalizer. 2. this input pin ignored and should be tied to gnd if the XRT75L03D has been configured to operate in the host mode. 3. these input pins are internally pulled low. system-side receive output and receive control pins p in #s ignal n ame t ype d escription
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 12 71 losmut/ int i/o muting upon los enable/interrupt output pin this input pin is used to configure the receive section, in each of the three channels within the chip, to automatically pull their corresponding recovered data output pins (e.g. rpos_n and rneg_n) to gnd anytime and for the duration that the receive section declares the los defect condition. in other words, this feature if enabled will cause the receive channel to automatically mute the recovered data anytime and for the duration that the receive section declares the los defect condition. "low" - disables the muting upon los feature. in this setting the receive sec- tion will not automatically mute the recovered data whenever it is declaring the los defect condition. "high" - enables the muting upon los feature. in this setting the receive sec- tion will automatically mute the recovered data whenever it is declaring the los defect condition. n otes : 1. this input pin is will function as the interrupt request output pin within the microprocessor serial interface, if the XRT75L03D has been configured to operate in the host mode. 2. this configuration setting applies globally to each of the three (3) channels within the XRT75L03D. 99 losthr i analog los detector threshold level select input: this input pin permits the user to select both of the following parameters for the analog los detector within each of the three receive sections within the XRT75L03D. 1. the analog los defect declaration threshold (e.g., the maximum signal level that the receive section of a given channel must detect before declaring the los defect condition), and 2. the analog los defect clearance threshold (e.g., the minimum signal level that the receive section of a given channel must detect before clearing the los defect condition) setting this input pin "high" selects one set of analog los defect declaration and clearance thresholds. setting this input pin "low" selects the other set of analog los defect declaration and clearance thresholds. please see table 10 for more details. n ote : this input pin is only active if at least one channel within the XRT75L03D has been configured to operate in the ds3 or sts-1 modes. system-side receive output and receive control pins p in #s ignal n ame t ype d escription
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 13 69 rxmon/ sdo i receiver monitor mode enable: this input pin permits the user to configure each of the three (3) receive sec- tions within the XRT75L03D, into the receiver monitor mode. if the user configures each of the receive sections into the receive monitor mode, then each of the receiver sections will be able to receive a nominal dsx-3/stsx-1 signal that has been attenuated by 20db of flat loss along with 6db of cable loss, in an error-free manner, and without declaring the los defect condition. "low" - configures each of the receive sections to operate in the normal mode. "high" - configures each of the receive sections to operate in the receive monitor mode. n otes : 1. this input pin will function as the sdo (serial data output pin within the microprocessor serial interface) whenever the XRT75L03D has been configured to operate in the host mode. 2. this configuration setting applies globally to all three (3) of the channels within the XRT75L03D. 68 rxon/ sdi i receive on: this input pin permits the user to either turn on or turn off each of the three (3) receive sections within the XRT75L03D. if the user turns on the receive sec- tions of each channel, then all three channels will begin to receive the incoming ds3, e3 or sts-1 data-streams via the rtip_n and rring_n input pins. conversely, if the user turns off the receive section, then the entire receive section (e.g., the agc and receive equalizer blocks, clock recovery pll, etc.) will be powered down. "low" - shuts off the receive sections within each of the three (3) channels in the XRT75L03D. "high" - turns on the receive sections within each of the three (3) channels in the XRT75L03D. n otes : 1. this input pin will function as the sdi (serial data input pin within the microprocessor serial interface) whenever the XRT75L03D has been configured to operate in the host mode. 2. this configuration setting applies globally to all three (3) of the channels within the XRT75L03D. 3. this pin is internally pulled low. system-side receive output and receive control pins p in #s ignal n ame t ype d escription
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 14 66 rxclkinv/ cs i receive clock invert input - chip selectl: in hardware mode is pin is used to configure the receive sections of the three (3) channels in the XRT75L03D to either output the recovered data via the rpos_n or rneg_n/lcv_n output pins upon either the rising or falling edge of the rclk_n clock output signal. "low" - configures each of the receive sections to output the recovered data via the rpos_n and rneg_n/lcv_n output pins upon the rising edge of the rclk_n output clock signal. "high" - configures each of the receive sections to output the recovered data via the rpos_n and rneg_n/lcv_n output pins upon the falling edge of the rclk_n output clock signal. n otes : 1. this input pin will function as the cs (chip select input pin) of the microprocessor serial interface when the XRT75L03D has been configured to operate in the host mode. 2. this configuration setting applies globally to all three (3) of the channels within the XRT75L03D. 3. if the receive sections are configured to operate in the single-rail mode, then the lcv_n output pin will be updated on the user-selected edge of the rclk_n signal, per this configuration selection. 106 sfm_en i single frequency mode enable: this input pin is used to configure the XRT75L03D to operate in the sfm (sin- gle frequency) mode. when this feature is invoked the single-frequency mode synthesizer will become active. by applying a 12.288mhz clock signal to pin 109, sts-1clk/ 12m the XRT75L03D will, depending upon which mode the user has configured each of the three channels, generate all of the appropriate clock signals (e.g., 34.368mhz, 44.736mhz or 51.84. further, the XRT75L03D internal circuitry will route each of these synthesized clock signals to the appropriate nodes of the corresponding three channels in the XRT75L03D. "low" - disables the single frequency mode. in this configuration setting, the user is required to supply to the e3clk, ds3clk or sts-1clk input pins all of the relevant clock signals that are to be used within the chip. "high" - enables the single-frequency mode. a 12.288mhz clock signal must be applied to pin 109 (sts-1clk/12m). n ote : this input pin is internally pulled low. system-side receive output and receive control pins p in #s ignal n ame t ype d escription
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 15 107 e3clk/ clk_en i e3 reference clock input/sfm clock output enable: the function of this chip depends upon whether or not the XRT75L03D has been configured to operate in the single-frequency mode. if not operating in the single-frequency mode if the XRT75L03D has not been configured to operate in the sfm (single fre- quency) mode, and if at least one channel is to be operated in the e3 mode, then a 34.368mhz clock signal must be applied to this input pin. if the user does not intend to operate the device in the sfm mode nor operate any of the channels in the e3 mode tie this input signal to gnd. if operating in the single-frequency mode if the XRT75L03D is operated in the sfm mode and is to output a clock signal that is synthesized from the sfm clock synthesizer pll so that the user's sys- tem can use this clock signal as a timing source, pull this input pin to a logic "high". if the user pull this input pin "high", then the XRT75L03D will output the line rate clock signal that has been synthesized for channel 1, via pin 108 (ds3clk/ clk_out). for example, if channel 1 is configured to operate in the sts-1 mode and this input pin is pulled "high", then the XRT75L03D will output a 51.84mhz clock signal via the clk_out pin. system-side receive output and receive control pins p in #s ignal n ame t ype d escription
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 16 108 ds3clk/ clk_out i/o ds3 reference clock input/sfm synthesizer clock output: the function of this chip depends upon whether or not the XRT75L03D has been configured to operate in the sfm mode. if not operating in the single-frequency mode if the XRT75L03D has not been configured to operate in the sfm mode, and if at least one channel of the XRT75L03D is configured in the ds3 mode, then a clock signal with a frequency of 44.736 mhz 20ppm must be applied to this input pin. if the XRT75L03D is not configured to operate in the sfm mode and none of the channels are to be operated in the ds3 mode, tie this input signal to gnd. if operating in the single-frequency mode if the XRT75L03D is configured to operate in the sfm mode, and if pin 107 (e3clk/clken) is pulled to a logic "high", then the sfm clock synthesizer pll generated line rate clock signal for channel 1 will be output via this output pin. in this mode, this particular output pin can be used by the user's system as a timing source. 109 sts-1clk/ 12m i sts-1 reference clock input/12.288mhz sfm reference clock input: the function of this pin depends upon whether or not the XRT75L03D has been configured to operate in the sfm mode. if not operating in the single-frequency mode if the XRT75L03D has not been configured to operate in the sfm mode and if at least one channel is intended to operate in the sts-1 mode, then the user must supply a clock signal with a frequency of 51.84mhz 4.6ppm to this input pin if the XRT75L03D is not to be operatedin the sfm mode and none of the chan- nels are to be operated in the sts-1 mode, tie this input signal to gnd. if operating in the single-frequency mode if the user has configured the XRT75L03D has been configured to operate in the sfm mode a clock signal with a frequency of 12.288mhz 20ppm must be applied to this input pin. the sfm synthesizer will then synthesize one of the appropriate line rate frequencies (e.g., 34.368mhz for e3, 44.736mhz for ds3, and 51.84mhz for sts-1) based upon this 12.288mhz reference clock source. system-side receive output and receive control pins p in #s ignal n ame t ype d escription
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 17 receive line side pins p in #s ignal n ame t ype d escription 79 91 88 rtip_0 rtip_1 rtip_2 i receive tip input - channel 0: receive tip input - channel 1: receive tip input - channel 2: these input pins along with the corresponding rring_n input pin function as the receive ds3/e3/sts-1 line input signal receiver for a given channel of the XRT75L03D. cconnect this signal and the corresponding rring_n input signal to a 1:1 transformer. whenever the rtip/rring input pins are receiving a positive-polarity pulse within the incoming ds3, e3 or sts-1 line signal, then this input pin will be pulsed to a "higher-voltage" than its corresponding rring_n input pin. conversely, whenever the rtip/rring input pins are receiving a negative- polarity pulse within the incoming ds3, e3 or sts-1 line signal, then this input pin will be pulsed to a "lower-voltage" than its corresponding rring_n input pin. 78 92 87 rring_0 rring_1 rring_2 i receive ring input - channel 0: receive ring input - channel 1: receive ring input - channel 2: these input pins along with the corresponding rtip_n input pin function as the receive ds3/e3/sts-1 line input signal receiver for a given channel of the XRT75L03D. connect this signal and the corresponding rtip_n input signal to a 1:1 trans- former. whenever the rtip/rring input pins are receiving a positive-polarity pulse within the incoming ds3, e3 or sts-1 line signal, then this input pin will be pulsed to a "lower-voltage" than its corresponding rtip_n input pin. conversely, whenever the rtip/rring input pins are receiving a negative- polarity pulse within the incoming ds3, e3 or sts-1 line signal, then this input pin will be pulsed to a "higher-voltage" than its corresponding rtip_n input pin.
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 18 clock interface p in #s ignal n ame t ype d escription 107 e3clk/ clk_en i e3 clock input (34.368 mhz 20 ppm): if all the 3 channels or any one of the channels is configured in e3 mode, a ref- erence clock 34.368 mhz 20 ppm is input to this pin.. clock output enable: if the single frequency mode is selected, tie this pin high to enable the clock output through the clk_out pin (pin 108). 108 ds3clk/ clk_out i/o ds3 clock input (44.736 mhz 20 ppm): if all the 3 channels or any one of the channels is configured in ds3 mode, a ref- erence clock 44.736 mhz 20 ppm is input to this pin. clock output: when the single frequency mode is enabled, this pin is configured as the clock output from channel 1.this clock frequency is determined by the channel 1 set- ting.. n ote : this low jitter output clock can be used as the input clock source for the framer device. thus eliminating the need for a separate clock source for the framer. 109 sts-1clk/ 12m i sts-1 clock input (51.84 mhz 20 ppm): if all the 3 channels or any one of the channels is configured in sts-1 mode, a reference clock 51.84 mhz 20 ppm is input to this pin. single frequency mode clock input: in single frequency mode, a reference clock of 12.288 mhz 20 ppm is con- nected to this pin and the internal clock synthesizer generates the appropriate clock frequencies based on the configuration of the rates (e3 or ds3 or sts-1).
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 19 general control pins p in #s ignal n ame t ype d escription 65 sr/dr i single-rail/dual-rail select input - chip level this input pin is used to configure the XRT75L03D to operate in either the sin- gle-rail or dual-rail mode. if the XRT75L03D is configured to operate in the single-rail mode, then all of the following will happen. ? all of the b3zs/hdb3 encoder and decoder blocks in the XRT75L03D will be enabled. ? the transmit section of each channel will accept all of the outbound data from the system-side equipment via the tpdata_n (or txdata_n) input pin. ? the receive section of each channel will output all of the recovered data to the system-side equipment via the rpos output pin. ? each of the rneg/lcv output pins will now function as the lcv (line code violation or excessive zero event) indicator output pin. if the user configures the device to operate in the dual-rail mode, then all of the following will happen. ? all of the b3zs/hdb3 encoder and decoder blocks in the XRT75L03D will be disabled. ? the transmit section of each channel will accept positive-polarity data via the tpdata_n input pin, and negative-polarity data via the tndata_n input pin. ? the receive section of each channel will pulse the rpos_n output pin "high" for one period of rclk_n for each time a positive-polarity pulse is received via the rtip_n/rring_n input pins ? likewise, the receive section of each channel will also pulse the rneg_n output pin "high" for one period of rclk_n for each time a negative-polarity pulse is received via the rtip_n/rring_n input pins. "low" - configures the XRT75L03D to operate in the dual-rail mode. "high" - configures the XRT75L03D to operate in the single-rail mode. n otes : 1. this input pin is ignored and should be tied to gnd if the XRT75L03D has been configured to operate in the host mode. 2. this pin is internally pulled "low". 76 94 85 e3_0 e3_1 e3_2 i e3 mode select input - channel 0 e3 mode select input - channel1 e3 mode select input - channel 2 this input pin, along with the corresponding sts-1/ds3 _n input pin is used the to configure a given channel within the XRT75L03D into either the ds3, e3 or sts-1 modes. "high" - configures the corresponding channel to operate in the e3 mode. "low" - configures the corresponding channel to operate in either the ds3 or sts-1 modes, depending upon the setting of the corresponding sts-1/ds3 _n input pin. n otes : 1. this input pin is ignored and should be tied to gnd if the XRT75L03D has been configured to operate in the host mode. 2. this input pin is internally pulled low.
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 20 72 98 81 sts-1/ds3 _0 sts-1/ds3 _1 sts-1/ds3 _2 i sts-1/ds3 select input - channel 0 sts-1/ds3 select input - channel 1 sts-1/ds3 select input - channel 2 this input pin, along with the corresponding e3_n input pin is used the to config- ure a given channel within the XRT75L03D into either the ds3, e3 or sts-1 modes. "high" - configures the corresponding channel to operate in the sts-1 mode provided that the corresponding e3_n input pin is pulled "low". "low" - configures the corresponding channel to operate in ds3 mode provided that the corresponding e3_n input pin is pulled "low". n otes : 1. this input pin is ignored and should be tied to gnd if the XRT75L03D has been configured to operate in the host mode or if the corresponding e3_n input pin is pulled "high". 2. this input pin is internally pulled low. 74 96 83 rlb_0 rlb_1 rlb_2 i remote loop-back - rlb input - channel 0: remote loop-back - rlb input - channel 1: remote loop-back - rlb input - channel 2: this input pin along with llb_n is used to configure different loop-back modes. n ote : this input pin is ignored and should be connected to gnd if the XRT75L03D is operating in the host mode. 73 97 82 llb_0 llb_1 llb_2 i loop-back select - llb input - channel 0 loop-back select - llb input - channel 1 loop-back select - llb input - channel 2 please see description above for rlb_n 102 test **** factory test mode input pin this pin must be connected to gnd for normal operation. n ote : this input pin is internally pulled "low". general control pins p in #s ignal n ame t ype d escription rlb_n 0 0 loopback mode normal (no loop-back) mode analog loop-back mode llb_n 0 1 1 1 remote loop-back mode digital local loop-back mode 0 1
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 21 62 ict i in-circuit test input : setting this pin "low" causes all digital and analog outputs to go into a high- impedance state to allow for in-circuit testing. for normal operation, set this pin "high". n ote : this pin is internally pulled high". 70 host/hw i host/hardware mode select: tie this pin high to configure the XRT75L03D in host mode. tie this low to configure in hardware mode. when the XRT75L03D is configured in host mode, the states of many of the discrete input pins are controlled by internal register bits. n ote : this pin is internally pulled up. control and alarm interface p in #s ignal n ame t ype d escription 122 rxa **** external resistor of 3.01k w 1%. should be connected between rxa and rxb for internal bias. 123 rxb **** external resistor of 3.01k w 1%. should be connected between rxa and rxb for internal bias. jitter attenuator interface p in #s ignal n ame t ype d escription 44 ja0 i jitter attenuator select 0: in hardware mode, this pin along with pin 42 configures the jitter attenuator as shown in the table below. n otes : 1. the setting of these input pins applies globally to all three (3) channels in the XRT75L03D. 2. this input pin is ignored and should be tied to gnd if the XRT75L03D is configured to operate in the host mode. general control pins p in #s ignal n ame t ype d escription 1 ja0 0 0 1 1 ja1 0 1 0 jitter attenuator disabled mode fifo depth = 16 bits fifo depth = 32 bits sonet/sdh de-sync mode
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 22 42 ja1 i jitter attenuator select 1: please see the description above for ja0 43 jatx/rx i jitter attenuator in transmit/receive path select input: this input pin is used to configure the jitter attenuator to operate in either the transmit or receive path within each of the three (3) channels of the XRT75L03D. "low" - configures the jitter attenuator within each channel to operate in the receive path. "high" - configures the jitter attenuator within each channel to operate in the transmit path. n otes : 1. the setting of this input pin applies globally to all three (3) channels of the XRT75L03D. 2. this input pin is ignored and should be tied to gnd if the XRT75L03D is configured to operate in the host mode or if the jitter attenuators are disabled. microprocessor serial interface - (host mode) p in #s ignal n ame t ype d escription 69 sdo/rxmon i/o microprocessor serial interface - serial data output: this pin serially outputs the contents of a specified on-chip command register during read operations via the microprocessor serial interface. the data which is output via this pin is updated upon the falling edge of the sclk clock signal. this output pin will be tri-stated upon completion of a given read operation. n ote : this pin functions as the rxmon input pin if the XRT75L03D has been configured to operate in the hardware mode. 68 sdi/rxon i microprocessor serial interface - serial data input: this input pin functions as the serial data input pin for the microprocessor serial interface. in particular, this input pin will accept all of the following data in a serial manner during read and write operations with the microprocessor serial interface. ? the read/write indicator bit. ? the address value of the targeted command register for this particular read or write operation. ? the data to be written into the targeted command register for a given write operation. all data that is applied to this input will be sampled upon the rising edge of the sclk input clock signal. n ote : this input pin will function as the rxon input pin if the XRT75L03D has been configured to operate in the hardware mode. jitter attenuator interface
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 23 67 sclk/tclkinv i microprocessor serial interface -serial clock input: this input pin functions as the clock source for the microprocessor serial inter- face. each time the user wishes to perform a read or write operate with the on- chip command registers via the microprocessor serial interface, the user must do the following. ? assert the cs input pin by toggling it "low", and ? provide 16 clock periods to this particular input pin for each read and write operation. the microprocessor serial interface will sample any data residing upon the sdi input pin, upon the rising edge of this clock signal. further, for read opera- tions, the microprocessor serial interface will serially output the contents of a target command register upon the falling edge of this clock signal. n ote : the maximum frequency of this particular clock signal is 10mhz. 66 cs /rclkinv i microprocessor serial interface - chip select input: this input pin should be pulled "low" whenever a read or write operation is to be executed to the on-chip command registers, via the microprocessor serial interface. this input pin should remain "low" until the read or write operation has been completed. this input pin should be pulled "high" at all other times. n ote : if the XRT75L03D has been configured to operate in the host mode then this input pin will function as the rclkinv input pin. 71 int /losmut o microprocessor serial interface - interrupt request output: if the XRT75L03D has been configured to operate in the host mode, then this pin becomes the interrupt request output for the XRT75L03D. during normal conditions, this output pin will be pulled "high". however, if the user enables certain interrupts within the device, and if those conditions occur, then the XRT75L03D will request an interrupt from the microprocessor by tog- gling this output pin "low". n otes : 1. if the XRT75L03D is configured to operate in the hardware mode, then this pin functions as the losmut input pin. 2. this pin will remain "low" until the interrupt has been served. 101 reset i microprocessor serial interface - h/w reset input: pulsing this input "low" causes the XRT75L03D to reset the contents of the on- chip command registers to their default values. as a consequence, the XRT75L03D will then also be operating in its default condition. for normal operation pull this input pin to a logic "high". n ote : this input pin is internally pulled high. microprocessor serial interface - (host mode) p in #s ignal n ame t ype d escription
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 24 power supply and ground pins p in #p in n ame t ype d escription r eceive a nalog vdd 77 93 86 rxavdd_0 rxavdd_1 rxavdd_2 **** t ransmit a nalog vdd 39 128 23 121 txavdd_0 txavdd_1 txavdd_2 refavdd **** j itter a ttenuator a nalog vdd 46 120 45 javdd_0 javdd_1 javdd_2 **** d igital vdd 29 12 20 55 111 54 119 110 txvdd_0 txvdd_1 txvdd_2 rxdvdd_0 rxdvdd_1 rxdvdd_2 jadvdd exdvdd ****
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 25 g rounds 41 126 15 80 90 89 47 118 48 49 116 100 124 27 14 18 59 115 50 117 105 txagnd_0 txagnd_1 txagnd_2 rxagnd_0 rxagnd_1 rxagnd_2 jagnd_0 jagnd_1 jagnd_2 agnd_0 agnd_1 agnd_2 refgnd txgnd_0 txgnd_1 txgnd_2 rxdgnd_0 rxdgnd_1 rxdgnd_2 jadgnd exdgnd **** power supply and ground pins p in #p in n ame t ype d escription
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 26 XRT75L03D pin listing in numerical order p in #p in n ame t ype c omments 1 txon_1 i this input pin is internally pulled high. 2tndata_1 i 3 tpdata_1 i 4tclk_1 i 5 mring_1 i 6mtip_1 i 7taos_1 i 1. not active while in host mode 2. this input pin is internally pulled low. 8taos_2 i 1. not active while in host mode 2. this input pin is internally pulled low. 9 txlev_1 i 1. not active while in host mode 2. this input pin is internally pulled low. 10 txlev_2 i 1. not active while in host mode 2. this input pin is internally pulled low. 11 ttip_1 o 12 dvdd *** 13 tring_1 o 14 txagnd_1 *** 15 txagnd_2 *** 16 mring_2 i 17 mtip_2 i 18 gnd *** 19 tring_2 o 20 txvdd_2 *** 21 ttip_2 o 22 dmo_2 o 23 txavdd_2 *** 24 tndata_2 i 25 tpdata_2 i 26 tclk_2 i 27 txgnd_0 *** 28 tring_0 o 29 txvdd_0 *** 30 ttip_0 o
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 27 31 mtip_0 i 32 mring_0 i 33 tndata_0 i 34 tpdata_0 i 35 taos_0 i not active while in host mode 36 txlev_0 i 1. not active while in host mode 2. this input pin is internally pulled low. 37 taos_0 i 1. not active while in host mode 2. this input pin is internally pulled low. 38 txon_0 i this input pin is internally pulled high. 39 txavdd_0 *** 40 dmo_0 o 41 txagnd_0 *** 42 ja1 i not active while in host mode 43 jatx/rx i not active while in host mode 44 ja0 i not active while in host mode 45 javdd_2 *** 46 javdd_0 *** 47 jagnd_0 *** 48 jagnd_2 *** 49 agnd_0 *** 50 rxdgnd_2 *** 51 rclk_2 o 52 rneg_2/lcv_2 o 53 rpos_2 o 54 rxdvdd_2 *** 55 rxdvdd_0 *** 56 rclk_0 o 57 rneg_0/lcv_0 o 58 rpos_0 o 59 rxdgnd_0 *** 60 rlos_0 o 61 rlol_0 o 62 ict i this input pin is internally pulled low. XRT75L03D pin listing in numerical order p in #p in n ame t ype c omments
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 28 63 rlos_2 o 64 rlol_2 o 65 sr/dr i 1. not active while in host mode 2. this input pin is internally pulled low. 66 rclkinv (cs )i 67 tclkinv (sclk) i 68 rxon (sdi) i this input pin is internally pulled low. 69 rxmon (sdo) i/o 70 host/hw i this input pin is internally pulled low. 71 losmut (int ) i/o 72 sts-1/ds3 _0 i 1. not active while in host mode 2. this input pin is internally pulled low. 73 llb_0 i not active while in host mode 74 rlb_0 i not active while in host mode 75 reqen_0 i 1. not active while in host mode 2. this input pin is internally pulled low. 76 e3_0 i 1. not active while in host mode 2. this input pin is internally pulled low. 77 rxavdd_0 *** 78 rring_0 i 79 rtip_0 i 80 rxagnd_0 *** 81 sts-1/ds3 _2 i 1. not active while in host mode 2. this input pin is internally pulled low. 82 llb_2 i not active while in host mode 83 rlb_2 i not active while in host mode 84 reqen_2 i 1. not active while in host mode 2. this input pin is internally pulled low. 85 e3_2 i 1. not active while in host mode 2. this input pin is internally pulled low. 86 rxavdd_2 *** 87 rring_2 i 88 rtip_2 i 89 rxagnd_2 *** 90 rxagnd_1 *** 91 rtip_1 i XRT75L03D pin listing in numerical order p in #p in n ame t ype c omments
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 29 92 rring_1 i 93 rxavdd_1 *** 94 e3_1 i 1. not active while in host mode 2. this input pin is internally pulled low. 95 reqen_1 i 1. not active while in host mode 2. this input pin is internally pulled low. 96 rlb_1 i not active while in host mode 97 llb_1 i not active while in host mode 98 sts-1/ds3 _1 i 1. not active while in host mode 2. this input pin is internally pulled low. 99 losthr i 100 agnd_2 *** 101 reset i this input pin is internally pulled high. 102 test i this input pin is internally pulled low. 103 rlol_1 o 104 rlos_1 o 105 exdgnd *** 106 sfm_en i this input pin is internally pulled low. 107 e3clk/clk_en i 108 ds3clk/ clk_out i/o 109 sts-1clk/12m i 110 exdvdd *** 111 rxdvdd_1 *** 112 rpos_1 o 113 rneg_1/lcv_1 o 114 rclk_1 o 115 rxdgnd_1 *** 116 agnd_1 *** 117 jadgnd *** 118 jagnd_1 *** 119 jadvdd *** 120 jadvdd_1 *** 121 refavdd *** 122 rxa *** XRT75L03D pin listing in numerical order p in #p in n ame t ype c omments
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 30 123 rxb *** 124 refgnd *** 125 txon_2 i this input pin is internally pulled high. 126 txagnd_1 *** 127 dmo_1 o 128 txavdd_1 *** XRT75L03D pin listing in numerical order p in #p in n ame t ype c omments
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 31 1.0 electrical characteristics n otes : 1. exposure to or operating near the min or max values for extended period may cause permanent failure and impair reliability of the device. 2. esd testing method is per mil-std-883d,m-3015.7 3. with linear air flow of 200 ft/min, reduce theta ja by 20%, theta jc is unchanged. n otes : 1. not applicable for pins with pull-up or pull-down resistors. 2. the digital inputs and outputs are ttl 5v compliant. t able 1: a bsolute m aximum r atings symbol p arameter min max units comments v dd supply voltage -0.5 6.0 v note 1 v in input voltage at any pin -0.5 5.5 v note 1 i in input current at any pin 100 ma note 1 s temp storage temperature -65 150 0 c note 1 a temp ambient operating temperature -40 85 0 c linear airflow 0 ft./min theta ja thermal resistance 23 0 c/w linear air flow 0ft/min (see note 3 below) m levl exposure to moisture 5 level eia/jedec jesd22-a112-a esd esd rating 2000 v note 2 t able 2: dc e lectrical c haracteristics : symbol p arameter min . typ . max . units dv dd digital supply voltage 3.135 3.3 3.465 v av dd analog supply voltage 3.135 3.3 3.465 v i cc supply current requirements 480 530 ma p dd power dissipation 1.3 1.5 w v il input low voltage 0.8 v v ih input high voltage 2.0 5.5 v v ol output low voltage, i out = - 4ma 0.4 v v oh output high voltage, i out = 4 ma 2.4 v i l input leakage current 1 10 m a c i input capacitance 10 pf c l load capacitance 10 pf
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 32 2.0 timing characteristics f igure 3. t ypical interface between terminal equipment and the XRT75L03D ( dual - rail data ) f igure 4. t ransmitter t erminal i nput t iming symbol parameter min typ max units txclk duty cycle e3 ds3 sts-1 30 50 34.368 44.736 51.84 70 % mhz mhz mhz t rtx txclk rise time (10% to 90%) 4 ns t ftx txclk fall time (10% to 90%) 4 ns t tsu tpdata/tndata to txclk falling set up time 3 ns t tho tpdata/tndata to txclk falling hold time 3 ns t tdy ttip/tring to txclk rising propagation delay time 8 ns terminal equipment (e3/ds3 or sts-1 framer) exar e3/ds3/sts-1 liu transmit logic block txpos txneg txlineclk tpdata tndata txclk tpdata or tndata ttip or tring txclk t tsu t tho t rtx t ftx t tdy
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 33 f igure 5. r eceiver d ata output and code violation timing symbol parameter min typ max units rxclk duty cycle e3 ds3 sts-1 45 50 34.368 44.736 51.84 55 % mhz mhz mhz t rrx rxclk rise time (10% o 90%) 2 4 ns t frx rxclk falling time (10% to 90%) 2 4 ns t co rxclk to rpos/rneg delay time 4 ns t lcvo rxclk to rising edge of lcv output delay 2.5 ns f igure 6. t ransmit p ulse a mplitude test circuit for e3, ds3 and sts-1 r ates rclk t rrx t frx rpos or rneg lcv t lcvo t co ttip(n) tring(n) XRT75L03D (0nly one channel shown) 1:1 r3 75 w txpos(n) txneg(n) txlineclk(n) tpdata(n) tndata(n) txclk(n) 37.4 w + 1% 37.4 w +1% r1 r2
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 34 3.0 line side characteristics: 3.1 e3 line side parameters: the XRT75L03D line output at the transformer output meets the pulse shape specified in itu-t g.703 for 34.368 mbits/s operation. the pulse mask as specified in itu-t g.703 for 34.368 mbits/s is shown in figure 7. f igure 7. p ulse m ask for e3 (34.368 mbits / s ) interface as per itu - t g.703 0% 50% v = 100% 14.55ns nominal pulse 12.1ns (14.55 - 2.45) 17 ns (14.55 + 2.45) 8.65 ns 10% 10% 20%
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 35 n ote : the above values are at ta = 25 0 c and v dd = 3.3 v 5%. t able 3: e3 t ransmitter line side output and receiver line side input specifications parameter min typ max units t ransmitter line side output characteristics transmit output pulse amplitude (measured at secondary of the transformer) 0.9 1.0 1.1 v pk transmit output pulse amplitude ratio 0.95 1.00 1.05 transmit output pulse width 12.5 14.55 16.5 ns transmit intrinsic jitter (without jitter attenuator in thetransmit path) 0.01 0.015 ui pp transmit intrinsic jitter ( with jitter attenuator in the transmit path) 0.02 0.03 ui pp r eceiver line side input characteristics receiver sensitivity (length of cable) 900 1200 feet interference margin -20 -14 db jitter tolerance @ jitter frequency 800khz 0.15 0.28 ui pp signal level to declare loss of signal -35 db signal level to clear loss of signal -15 db occurence of los to los declaration time 10 255 ui termination of los to los clearance time 10 255 ui
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 36 f igure 8. b ellcore gr-253 core t ransmit o utput p ulse t emplate for sonet sts-1 a pplications t able 4: sts-1 p ulse m ask e quations t ime in u nit i ntervals n ormalized a mplitude lower curve -0.85 < t < -0.38 - 0.03 -0.38 < t < 0.36 0.36 < t < 1.4 - 0.03 upper curve -0.85 < t < -0.68 0.03 -0.68 < t < 0.26 0.26 < t < 1.4 0.1 + 0.61 x e -2.4[t-0.26] sts-1 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 time, in ui normalized amplitude lower curve upper curve 0.5 1 p 2 -- -1 t 0.18 ----------- + ? ? ? ?t y sin + 0.03 C 0.5 1 p 2 -- -1 t 0.34 ----------- + ? ? ? ?t y sin + 0.03 +
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 37 n ote : the above values are at ta = 25 0 c and v dd = 3.3 v 5%. t able 5: sts-1 t ransmitter l ine s ide o utput and r eceiver l ine s ide i nput s pecifications (gr-253) p arameter m in t yp m ax u nits t ransmitter line side output characteristics transmit output pulse amplitude (measured with txlev = 0) 0.65 0.75 0.9 v pk transmit output pulse amplitude (measured with txlev = 1) 0.9 1.0 1.1 v pk transmit output pulse width 8.6 9.65 10.6 ns transmit output pulse amplitude ratio 0.9 1.0 1.1 transmit intrinsic jitter ( without jitter attenuator in transmit path) 0.01 0.015 ui pp transmit intrinsic jitter ( with jitter attenuator in transmit path) 0.02 0.04 ui pp r eceiver line side input characteristics receiver sensitivity (length of cable) 900 1100 feet jitter tolerance @ jitter frequency 400 khz 0.15 ui pp signal level to declare loss of signal refer to table 10 signal level to clear loss of signal refer to table 10
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 38 f igure 9. t ransmit o uput p ulse t emplate for ds3 as per b ellcore gr-499 t able 6: ds3 p ulse m ask e quations t ime in u nit i ntervals n ormalized a mplitude lower curve -0.85 < t < -0.36 - 0.03 -0.36 < t < 0.36 0.36 < t < 1.4 - 0.03 upper curve -0.85 < t < -0.68 0.03 -0.68 < t < 0.36 0.36 < t < 1.4 0.08 + 0.407 x e -1.84[t-0.36] ds3 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 tim e, in ui normalized amplitude lower curve upper curve 0.5 1 p 2 -- -1 t 0.18 ----------- + ? ? ? ?t y sin + 0.03 C 0.5 1 p 2 -- -1 t 0.34 ----------- + ? ? ? ?t y sin + 0.03 +
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 39 n ote : the above values are at ta = 25 0 c and v dd = 3.3v 5%. n ote : if the r/w bit is set to "1", then this denotes a "read" operation with the microprocessor serial interface. conversely, if the r/w bit is set to "0", then this denotes a "write" operation. t able 7: ds3 t ransmitter l ine s ide o utput and r eceiver l ine s ide i nput s pecifications (gr-499) p arameter m in t yp m ax u nits t ransmitter line side output characteristics transmit output pulse amplitude (measured with txlev = 0) 0.65 0.75 0.85 v pk transmit output pulse amplitude (measured with txlev = 1) 0.9 1.0 1.1 v pk transmit output pulse width 10.10 11.18 12.28 ns transmit output pulse amplitude ratio 0.9 1.0 1.1 transmit intrinsic jitter ( without jitter attenuator in transmit path) 0.01 0.015 ui pp transmit intrinsic jitter ( withjitter attenuator in transmit path) 0.02 0.04 ui pp r eceiver line side input characteristics receiver sensitivity (length of cable) 900 1100 feet jitter tolerance @ 400 khz (cat ii) 0.15 ui pp signal level to declare loss of signal refer to table 10 signal level to clear loss of signal refer to table 10 f igure 10. m icroprocessor s erial i nterface s tructure d0 d1 d2 d7 d6 d5 d4 d3 high z sdo a0 d0 r/w d1 0 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 sdi 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sclk cs high z
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 40 f igure 11. t iming d iagram for the m icroprocessor s erial i nterface t able 8: m icroprocessor s erial i nterface t imings ( t a = 25 0 c, v dd =3.3v 5% and load = 10 p f) s ymbol p arameter m in .t yp .m ax u nits t 21 cs low to rising edge of sclk 5 ns t 22 sdi to rising edge of sclk 5 ns t 23 sdi to rising edge of sclk hold time 5 ns t 24 sclk "low" time 50 ns t 25 sclk "high" time 50 ns t 26 sclk period 100 ns t 27 falling edge of sclk to rising edge of cs 0ns t 28 cs inactive time 50 ns t 29 falling edge of sclk to sdo valid time 20 ns t 30 falling edge of sclk to sdo invalid time 10 ns t 31 rising edge of cs to high z 25 ns t 32 rise/fall time of sdo output 5 ns sdi r/w a1 a0 cs sclk cs sclk sdi sdo d0 d1 d2 d7 t 21 t 22 t 23 t 24 t 25 t 26 t 27 t 28 t 29 t 30 t 31 t 32 hi-z hi-z
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 41 functional description: figure 1 shows the functional block diagram of the device. each channel can be independently configured either by hardware mode or by host mode to support e3, ds3 or sts-1 modes. a detailed operation of each section is described below. each channel consists of the following functional blocks: 4.0 the transmitter section: the transmitter section, within each channel, accepts ttl/cmos level signals from the terminal equipment in selectable data formats. convert the cmos level b3zs or hdb3 encoded data into pulses with shapes that are compliant with the various industry standard pulse template requirements. figures 7, 8 and 9 illustrate the pulse template requirements. encode the un-encoded nrz data into either b3zs format for (ds3 or sts-1) or hdb3 format (for e3) and convert to pulses with shapes and width that are compliant with industry standard pulse template requirements. figures 7, 8 and 9 illustrate the pulse template requirements. in single-rail or un-encoded non-return-to-zero (nrz) mode, data is input via tpdata_n pins while tndata_n pins must be grounded. the nrz or single-rail mode is selected when the sr/dr input pin is high (in hardware mode) or bit 0 of channel control register is 1 (in host mode). figure 12 illustrates the single-rail or nrz format. in dual-rail mode, data is input via tpdata_n and tndata_n pins. tpdata_n contains positive data and tndata_n contains negative data. the sr/dr input pin = low (in hardware mode) or bit 0 of channel register = 0 (in host mode) enables the dual-rail mode. figure 13 illustrates the dual-rail data format. f igure 12. s ingle -r ail or nrz d ata f ormat (e ncoder and d ecoder are e nabled ) f igure 13. d ual -r ail d ata f ormat ( encoder and decoder are disabled ) txclk tpdata data 1 1 0 txclk tpdata tndata data 1 1 0
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 42 4.1 t ransmit c lock : the transmit clock applied via txclk_n pins, for the selected data rate (for e3 = 34.368 mhz, ds3 = 44.736 mhz or sts-1 = 51.84 mhz), is duty cycle corrected by the internal pll circuit to provide a 50% duty cycle clock to the pulse shaping circuit. this allows a 30% to 70% duty cycle transmit clock to be supplied. 4.2 b3zs/hdb3 e ncoder : when the single-rail (nrz) data format is selected, the encoder block encodes the data into either b3zs format (for either ds3 or sts-1) or hdb3 format (for e3). 4.2.1 b3zs encoding: an example of b3zs encoding is shown in figure 14. if the encoder detects an occurrence of three consecutive zeros in the data stream, it is replaced with either b0v or 00v, where b refers to bipolar pulse that is compliant with the alternating polarity requirement of the ami (alternate mark inversion) line code and v refers to a bipolar violation (e.g., a bipolar pulse that violates the ami line code). the substitution of b0v or 00v is made so that an odd number of bipolar pulses exist between any two consecutive violation (v) pulses. this avoids the introduction of a dc component into the line signal. 4.2.2 hdb3 encoding: an example of the hdb3 encoding is shown in figure 15. if the hdb3 encoder detects an occurrence of four consecutive zeros in the data stream, then the four zeros are substituted with either 000v or b00v pattern. the substitution code is made in such a way that an odd number of bipolar (b) pulses exist between any consecutive v pulses. this avoids the introduction of dc component into the analog signal. f igure 14. b3zs e ncoding f ormat f igure 15. hdb3 e ncoding f ormat 000 1 1 1 1 1 1 1 v b v 1 0 00 00 0 0 0 0 0 0 0 0 000 v bv 0 00 tclk line signal tpdata 0 0 000 1 1 1 1 1 1 1 v b v 1 0 00 00 0 0 0 0 0 0 0 0 00 v b 0 00 tclk line signal tpdata
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 43 n otes : 1. when dual-rail data format is selected, the b3zs/hdb3 encoder is automatically disabled. 2. in dual-rail format, the bipolar violations in the incoming data stream is converted to valid data pulses. 3. encoder and decoder is enabled only in single-rail mode. 4.3 t ransmit p ulse s haper : the transmit pulse shaper converts the b3zs encoded digital pulses into a single analog alternate mark inversion (ami) pulse that meet the industry standard mask template requirements for sts-1 and ds3. see figures 8 and 9. for e3 mode, the pulse shaper converts the hdb3 encoded pulses into a single full amplitude square shaped pulse with very little slope. this is illustrated in figure 7. the pulse shaper block also includes a transmit build out circuit, which can either be disabled or enabled by setting the txlev_n input pin high or low (in hardware mode) or setting the txlev_n bit to 1 or 0 in the control register (in host mode). for ds3/sts-1 rates, the transmit build out circuit is used to shape the transmit waveform that ensures that transmit pulse template requirements are met at the cross-connect system. the distance between the transmitter output and the cross-connect system can be between 0 to 450 feet. for e3 rate, since the output pulse template is measured at the secondary of the transformer and since there is no cross-connect system pulse template requirements, the transmit build out circuit is always disabled. 4.3.1 guidelines for using transmit build out circuit: if the distance between the transmitter and the dsx3 or stsx-1, cross-connect system, is less than 225 feet, enable the transmit build out circuit by setting the txlev_n input pin low (in hardware mode) or setting the txlev_n control bit to 0 (in host mode). if the distance between the transmitter and the dsx3 or stsx-1 is greater than 225 feet, disable the transmit build out circuit. 4.3.2 interfacing to the line: the differential line driver increases the transmit waveform to appropriate level and drives into the 75 w load as shown in figure 6.
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 44 4.4 transmit drive monitor: this feature is used for monitoring the transmit line for occurrence of fault conditions such as a short circuit on the line or a defective line driver. to activate this function, connect mtip_n pins to the ttip_n lines via a 270 w resistor and mring_n pins to tring_n lines via 270 w resistor as shown in figure 16. when the mtip_n and mring_n are connected to the ttip_n and tring_n lines, the drive monitor circuit monitors the line for transitions. the dmo_n (drive monitor output) will be asserted low as long as the transitions on the line are detected via mtip_n and mring_n. if no transitions on the line are detected for 128 32 txclk_n periods, the dmo_n output toggles high and when the transitions are detected again, dmo_n toggles low. n ote : the drive monitor circuit is only for diagnostic purpose and does not have to be used to operate the transmitter. 4.5 transmitter section on/off: the transmitter section of each channel can either be turned on or off. to turn on the transmitter, set the input pin txon_n to high (in hardware mode) or write a 1 to the txon_n control bits (in host mode) and txon_n pins tied high. when the transmitter is turned off, ttip_n and tring_n are tri-stated. n otes : 1. this feature provides support for redundancy. 2. if the XRT75L03D is configured in host mode, to permit a system designed for redundancy to quickly shut-off the defective line card and turn on the back-up line card, writing a 1 to the txon_n control bits transfers the control to txon_n pins. 5.0 the receiver section: this section describes the detailed operation of the various blocks in the receiver. the receiver recovers the ttl/cmos level data from the incoming bipolar b3zs or hdb3 encoded input pulses. 5.1 agc/equalizer: the adaptive gain control circuit amplifies the incoming analog signal and compensates for the various flat losses and also for the loss at one-half symbol rate. the agc has a dynamic range of 30 db. the equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation of up to 900 feet of coaxial cable (1300 feet for e3). the equalizer also boosts the high frequency content of the f igure 16. t ransmit d river m onitor set - up . ttip(n) tring(n) XRT75L03D (0nly one channel shown) 1:1 r3 75 w txpos(n) txneg(n) txlineclk(n) tpdata(n) tndata(n) txclk(n) 37.4 w + 1% 37.4 w +1% r1 r2 mring(n) mtip(n) r5 270 w r4 270 w
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 45 signal to reduce inter-symbol interference (isi) so that the slicer slices the signal at 50% of peak voltage to generate positive and negative data. the equalizer can either be in or out by setting the reqen_n pin high or low (in hardware mode) or setting the reqen_n control bit to 1 or 0 (in host mode). r ecommendations for e qualizer s ettings : the equalizer has two gain settings to provide optimum equalization. in the case of normally shaped ds3/ sts-1 pulses (pulses that meet the template requirements) that has been driven through 0 to 900 feet of cable, the equalizer can be left in by setting the reqen_n pin to high (in hardware mode) or setting the reqen_n control bit to 1 (in host mode). however, for square-shaped pulses such as e3 or for ds3/sts-1 high pulses (that does not meet the pulse template requirements), it is recommended that the equalizer be left out for cable length less than 300 feet by setting the reqen_n pin low (in hardware mode) or by setting the reqen_n control bit to 0 (in host mode).this would help to prevent over-equalization of the signal and thus optimize the performance in terms of better jitter transfer characteristics. n ote : the results of extensive testing indicates that even when the equalizer was left in (reqen_n = high), regardless of the cable length, the integrity of the e3 signal was restored properly over 0 to 12 db cable loss at industrial temperature. the equalizer also contain an additional 20 db gain stage to provide the line monitoring capability of the resistively attenuated signals which may have 20db flat loss. this capability can be turned on by writing a 1 to the rxmon_n bits in the control register or by setting the rxmon pin (pin 69) high. 5.1.1 interference tolerance: for e3 mode, itu-t g.703 recommendation specifies that the receiver be able to recover error-free clock and data in the presence of a sinusoidal interfering tone signal. for ds3 and sts-1 modes, the same recommendation is being used. figure 17 shows the configuration to test the interference margin for ds3/ sts1. figure 18 shows the set up for e3. f igure 17. i nterference m argin t est s et up for ds3/sts-1 ? test equipment pattern generator 2 23 -1 prbs sine wave generator n s 0 to 900 feet coaxial cable dut XRT75L03D attenuator ds3 = 22.368 mhz sts-1 = 25.92 mhz
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 46 5.2 clock and data recovery: the clock and data recovery circuit extracts the embedded clock, rxclk_n from the sliced digital data stream and provides the retimed data to the b3zs (hdb3) decoder. the clock recovery pll can be in one of the following two modes: t raining m ode : in the absence of input signals at rtip_n and rring_n pins, or when the frequency difference between the recovered line clock signal and the reference clock applied on the exclk_n input pins exceed 0.5%, a loss of lock condition is declared by toggling rlol_n output pin high (in hardware mode) or setting the rlol_n bit to 1 in the control registers (in host mode). also, the clock output on the rxclk_n pins are the same as the reference clock applied on exclk_n pins. d ata /c lock r ecovery m ode : in the presence of input line signals on the rtip_n and rring_n input pins and when the frequency difference between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on the rxclk_n out pins is the recovered clock signal. f igure 18. i nterference m argin t est s et up for e3. t able 9: i nterference m argin t est r esults m ode c able l ength (a ttenuation )i nterference t olerance e3 0 db equalizer in -17 db 12 db -14 gb ds3 0 feet -15 db 225 feet -15 db 450 feet -14 db sts-1 0 feet -15 db 225 feet -14 db 450 feet -14 db ? test equipment noise generator 2 23 -1 prbs signal source n s 0 to 12 db cable loss dut XRT75L03D attenuator 1 attenuator 2
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 47 5.3 b3zs/hdb3 decoder: the decoder block takes the output from clock and data recovery block and decodes the b3zs (for ds3 or sts-1) or hdb3 (for e3) encoded line signal and detects any coding errors or excessive zeros in the data stream. whenever the input signal violates the b3zs or hdb3 coding sequence for bipolar violation or contains three (for b3zs) or four (for hdb3) or more consecutive zeros, an active high pulse is generated on the rlcv_n output pins to indicate line code violation. n ote : in dual-rail mode, the decoder is bypassed. 5.4 los (loss of signal) detector: 5.4.1 ds3/sts-1 los condition: a digital loss of signal (dlos) condition occurs when a string of 175 75 consecutive zeros occur on the line. when the dlos condition occurs, the dlos_n bit is set to 1 in the status control register. dlos condition is cleared when the detected average pulse density is greater than 33% for 175 75 pulses. analog loss of signal (alos) condition occurs when the amplitude of the incoming line signal is below the threshold as shown in the table 10.the status of the alos condition is reflected in the alos_n status control register. rlos is the logical or of the dlos and alos states. when the rlos condition occurs the rlos_n output pin is toggled high and the rlos_n bit is set to 1 in the status control register. d isabling alos/dlos d etection : for debugging purposes it is useful to disable the alos and/or dlos detection. writing a 1 to both alosdis_n and dlosdis_n bits disables the los detection on a per channel basis. 5.4.2 e3 los condition: if the level of incoming line signal drops below the threshold as described in the itu-t g.775 standard, the los condition is detected. loss of signal level is defined to be between 15 and 35 db below the normal level. if the signal drops below 35 db for 10 to 255 consecutive pulse periods, los condition is declared. this is illustrated in figure 19. t able 10: t he alos (a nalog los) d eclaration and c learance t hresholds for a given setting of losthr and reqen (ds3 and sts-1 a pplications ) a pplication reqen s etting losthr s etting s ignal l evel to d eclare alos d efect s ignal l evel to c lear alos d efect ds3 0 0 < 75mvpk > 130mvpk 1 0 < 45mvpk > 60mvpk 0 1 < 120mvpk > 45mvpk 1 1 < 55mvpk > 180mvpk sts-1 0 0 < 120mvpk > 170mvpk 1 0 < 50mvpk > 75mvpk 0 1 < 125mvpk > 205mvpk 1 1 < 55mvpk > 90mvpk
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 48 as defined in itu-t g.775, an los condition is also declared between 10 and 255 ui (or e3 bit periods) after the actual time the los condition has occurred. the los condition is cleared within 10 to 255 ui after restoration of the incoming line signal. figure 20 shows the los declaration and clearance conditions. f igure 19. l oss o f s ignal d efinition for e3 as per itu-t g.775 f igure 20. l oss of s ignal d efinition for e3 as per itu-t g.775. 0 db -12 db -15db -35db maximum cable loss for e3 los signal must be declared los signal must be cleared los signal may be cleared or declared actual occurrence of los condition line signal is restored time range for los declaration time range for los clearance g.775 compliance g.775 compliance 0 ui 10 ui 0 ui 10 ui 255 ui 255 ui rtip/ rring rlos output pin
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 49 5.4.3 muting the recovered data with los condition: when the los condition is declared, the clock recovery circuit locks into the reference clock applied to the exclk_n pin and output this clock on the rxclk_n output.in single frequency mode (sfm), the clock recovery locks into the rate clock generated and output this clock on the rxclk_n pins. the data on the rpos_n and rneg_n pins can be forced to zero by pulling the losmut pin high (in hardware mode) or by setting the losmut_n bits in the individual channel control register to 1 (in host mode). n ote : when the los condition is cleared, the recovered data is output on rpos_n and rneg_n pins. 6.0 jitter: there are three fundamental parameters that describe circuit performance relative to jitter: jitter tolerance (receiver) jitter transfer (receiver/transmitter) jitter generation 6.1 j itter t olerance - r eceiver : jitter tolerance is a measure of how well a clock and data recovery unit can successfully recover data in the presence of various forms of jitter. it is characterized by the amount of jitter required to produce a specified bit error rate. the tolerance depends on the frequency content of the jitter. jitter tolerance is measured as the jitter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error rate (ber). to measure the jitter tolerance as shown in figure 21, jitter is introduced by the sinusoidal modulation of the serial data bit sequence. input jitter tolerance requirements are specified in terms of compliance with jitter mask which is represented as a combination of points.each point corresponds to a minimum amplitude of sinusoidal jitter at a given jitter frequency. 6.1.1 ds3/sts-1 jitter tolerance requirements: bellcore gr-499 core, issue 1, december 1995 specifies the minimum requirement of jitter tolerance for category i and category ii. the jitter tolerance requirement for category ii is the most stringent. figure 22 shows the jitter tolerance curve as per gr-499 specification. f igure 21. j itter t olerance m easurements freq synthesizer pattern generator dut XRT75L03D error detector modulation freq. data clock
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 50 6.1.2 e3 jitter tolerance requirements: itu-t g.823 standard specifies that the clock and data recovery unit must be able to accommodate and tolerate jitter up to certain specified limits. figure 23 shows the tolerance curve. as shown in the figures 22 and 23 above, in the jitter tolerance measurement, the dark line indicates the minimum level of jitter that the e3/ds3/sts-1 compliant component must tolerate. the table 11 below shows the jitter amplitude versus the modulation frequency for various standards. f igure 22. i nput j itter t olerance f or ds3/sts-1 f igure 23. i nput j itter t olerance for e3 0.01 0.03 15 1.5 0.3 2 20 0.15 jitter amplitude (ui pp ) jitter frequency (khz) 10 5 0.3 100 0.1 gr-253 sts-1 g r-499 cat ii g r-499 cat i 64 41 XRT75L03D 0.1 1.5 1 10 jitter amplitude (ui pp ) jitter frequency (khz) 800 itu-t g.823 64 10 0.3 XRT75L03D
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 51 6.2 j itter t ransfer - r eceiver /t ransmitter : jitter transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input versus frequency. there are two distinct characteristics in jitter transfer: jitter gain (jitter peaking) defined as the highest ratio above 0db; and jitter transfer bandwidth.the overall jitter transfer bandwidth is controlled by a low bandwidth loop, typically using a voltage-controller crystal oscillator (vcxo). the jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often expressed in db. a negative db jitter transfer indicates the element removed jitter. a positive db jitter transfer indicates the element added jitter.a zero db jitter transfer indicates the element had no effect on jitter. table 12 shows the jitter transfer characteristics and/or jitter attenuation specifications for various data rates: the above specifications can be met only with a jitter attenuator that supports e3/ds3/sts-1 rates. 6.3 jitter attenuator: an advanced crystal-less jitter attenuator per channel is included in the XRT75L03D. the jitter attenuator requires no external crystal nor high-frequency reference clock. in host mode, by clearing or setting the jatx/rx_n bits in the channel control registers selects the jitter attenuator either in the receive or transmit path on per channel basis. in hardware mode, jatx/rx pin selects globally all three channels either in receive or transmit path. the fifo size can be either 16-bit or 32-bit. in host mode, the bits ja0_n and ja1_n can be set to appropriate combination to select the different fifo sizes or to disable the jitter attenuator on a per channel basis. in hardware mode, appropriate setting of the pins ja0 and ja1 selects the different fifo sizes or disables the jitter attenuator for all three channels. data is clocked into the fifo with the associated clock signal (txclk or rxclk) and clocked out of the fifo with the dejittered clock. when the fifo is within two bits of overflowing or underflowing, the fifo limit status bit, fl_n is set to 1 in the alarm status register. reading this bit clears the fifo and resets the bit into default state. n ote : it is recommended to select the 16-bit fifo for delay-sensitive applications as well as for removing smaller amounts of jitter. table 13 specifies the jitter transfer mask requirements for various data rates: t able 11: j itter a mplitude versus m odulation f requency (j itter t olerance ) b it r ate ( kb / s ) s tandard i nput j itter a mplitude (ui p - p ) m odulation f requency a1 a2 a3 f 1(h z ) f 2(h z ) f 3( k h z ) f 4( k h z ) f 5( k h z ) 34368 itu-t g.823 1.5 0.15 - 100 1000 10 800 - 44736 gr-499 core cat i 5 0.1 - 10 2.3k 60 300 - 44736 gr-499 core cat ii 10 0.3 - 10 669 22.3 300 - 51840 gr-253 core cat ii 15 1.5 0.15 10 30 300 2 20 t able 12: j itter t ransfer s pecification /r eferences e3 ds3 sts-1 etsi tbr-24 gr-499 core section 7.3.2 category i and category ii gr-253 core section 5.6.2.1
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 52 the jitter attenuator within the XRT75L03D meets the latest jitter attenuation specifications and/or jitter transfer characteristics as shown in the figure 24. 6.3.1 j itter g eneration : jitter generation is defined as the process whereby jitter appears at the output port of the digital equipment in the absence of applied input jitter. jitter generation is measured by sending jitter free data to the clock and data recovery circuit and measuring the amount of jitter on the output clock or the re-timed data. since this is essentially a noise measurement, it requires a definition of bandwidth to be meaningful. the bandwidth is set according to the data rate. in general, the jitter is measured over a band of frequencies. 7.0 serial host interface: a serial microprocessor interface is included in the XRT75L03D. the interface is generic and is designed to support the common microprocessors/microcontrollers. the XRT75L03D operates in host mode when the host/hw pin is tied high. the serial interface includes a serial clock (sclk), serial data input (sdi), serial data output (sdo), chip select (cs) and interrupt output (int). the serial interface timing is shown in figure 11. the active low interrupt output signal (int pin) indicates alarm conditions like los, dmo and fl to the processor. t able 13: j itter t ransfer p ass m asks r ate ( kbits ) m ask f1 (h z ) f2 (h z ) f3 (h z ) f4 ( k h z ) a1(db) a2(db) 34368 g.823 etsi-tbr-24 100 300 3 k 800 k 0.5 -19.5 44736 gr-499, cat i gr-499, cat ii gr-253 core 10 10 10 10k 56.6k 40 - - - 15k 300k 15k 0.1 0.1 0.1 - - - 51840 gr-253 core 10 40k - 400k 0.1 - f igure 24. j itter t ransfer r equirements and j itter a ttenuator p erformance f1 a1 f2 jitter amplitude jitter frequency (khz) a2 f3 f4
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 53 when the XRT75L03D is configured in host mode, the following input pins,txlev_n, taos_n, rlb_n, llb_n, e3_n, sts-1/ds3_n, reqen_n, jatx/rx, ja0 and ja1 are disabled and must be connected to ground. the table 14 below illustrates the functions of the shared pins in either host mode or in hardware mode. n ote : while configured in host mode, the txon_n input pins will be active if the txon_n bits in the control register are set to 1, and can be used to turn on and off the transmit output drivers. this permits a system designed for redundancy to quickly switch out a defective line card and switch-in the backup line card. t able 14: f unctions of shared pins p in n umber i n h ost m ode i n h ardware m ode 66 cs rxclkinv 67 sclk txclkinv 68 sdi rxon 69 sdo rxmon 71 int losmut
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 54 t able 15: XRT75L03D r egister m ap - q uick l ook a ddress l ocation r egister n ame b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 0x00 aps/redundancy control register reserved rxon ch 2 rxon ch 1 rxon ch 0 reserved txon ch 2 txon ch 1 txon ch 0 c hannel 0 r egisters 0x01 source level interrupt enable register - ch 0 reserved change of fl alarm condition interrupt enable change of rlol condition interrupt enable change of rlos defect condition interrupt enable change of dmo condition interrupt enable 0x02 source level interrupt status register - ch 0 reserved change of fl alarm condition interrupt status change of rlol condition interrupt status change of rlos condition interrupt status change of dmo condition interrupt status 0x03 alarm status register - ch 0 reserved loss of prbs pattern sync dlos defect declared alos defect declared fl alarm declared rlol condition declared rlos defect condition dmo condition status 0x04 transmit control register - ch 0 reserved internal transmit drive monitoring insert prbs error unused ta o s txclk inv txlev 0x05 receive control register - ch 0 reserved disabled- los detector disablea- los detec- tor rxclk inv losmuten- able receive monitor mode enable receive equalizer enable 0x06 channel control register - ch 0 reserved prbs enable rlb llb e3 mode sts-1/ds3 mode sr/dr mode 0x07 jitter attenuator control register - ch 0 reserved sonet aps recovery time mode disable ja reset ja1 (ja mode select bit 1) ja in txpath ja0 (ja mode select 0) c hannel 1 r egisters 0x08 reserved reserved reserved reserved reserved reserved reserved 0x09 source level interrupt enable register - ch 0 reserved change of fl alarm condition interrupt enable change of rlol condition interrupt enable change of rlos defect condition interrupt enable change of dmo condition interrupt enable 0x0a source level interrupt status register - ch 0 reserved change of fl alarm condition interrupt status change of rlol condition interrupt status change of rlos condition interrupt status change of dmo condition interrupt status
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 55 0x0b alarm status register - ch 0 reserved loss of prbs pattern sync dlos defect declared alos defect declared fl alarm declared rlol condition declared rlos defect condition dmo condition status 0x0c transmit control register - ch 0 reserved internal transmit drive monitoring insert prbs error unused ta o s txclk inv txlev 0x0d receive control register - ch 0 reserved disabled- los detector disablea- los detec- tor rxclk inv losmuten- able receive monitor mode enable receive equalizer enable 0x0e channel control register - ch 0 reserved prbs enable rlb llb e3 mode sts-1/ds3 mode sr/dr mode 0x0f jitter attenuator control register - ch 0 reserved sonet aps recovery time mode disable ja reset ja1 (ja mode select bit 1) ja in txpath ja0 (ja mode select 0) c hannel 2 r egisters 0x10 reserved reserved reserved reserved reserved reserved reserved 0x11 source level interrupt enable register - ch 0 reserved change of fl alarm condition interrupt enable change of rlol condition interrupt enable change of rlos defect condition interrupt enable change of dmo condition interrupt enable 0x12 source level interrupt status register - ch 0 reserved change of fl alarm condition interrupt status change of rlol condition interrupt status change of rlos condition interrupt status change of dmo condition interrupt status 0x13 alarm status register - ch 0 reserved loss of prbs pattern sync dlos defect declared alos defect declared fl alarm declared rlol condition declared rlos defect condition dmo condition status 0x14 transmit control register - ch 0 reserved internal transmit drive monitoring insert prbs error unused ta o s txclk inv txlev 0x15 receive control register - ch 0 reserved disabled- los detector disablea- los detec- tor rxclk inv losmuten- able receive monitor mode enable receive equalizer enable 0x16 channel control register - ch 0 reserved prbs enable rlb llb e3 mode sts-1/ds3 mode sr/dr mode t able 15: XRT75L03D r egister m ap - q uick l ook a ddress l ocation r egister n ame b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 56 the register map and description for the XRT75L03D 3-channel ds3/e3/sts-1 liu ic 0x17 jitter attenuator control register - ch 0 reserved sonet aps recovery time mode disable ja reset ja1 (ja mode select bit 1) ja in txpath ja0 (ja mode select 0) 0x19 - 0x1f reserved reserved 0x20 block level interrupt enable register - ch 32 0x21 block level interrupt enable register - ch 33 0x22 - 0x3d reserved reserved 0x3e device part number register 0 1 1 1 0 0 1 1 0x3f chip revision number register 0 0 0 0 revision number value 0x40 - 0xff reserved reserved l egend : denotes reserved (or unused) register bits denotes read/write bits denotes read-only bits denotes reset-upon-read bits t able 16: c ommand r egister a ddress m ap , within the XRT75L03D 3-c hannel ds3/e3/sts-1 liu w / j itter a ttenuator ic a ddress c ommand r egister t ype r egister n ame 0x00 cr0 r/w aps/redundancy control register c hannel 0 c ontrol r egisters 0x01 cr1 r/o source level interrupt enable register - channel 0 0x02 cr2 r/w source level interrupt status register channel 0 0x03 cr3 r/o alarm status register - channel 0 t able 15: XRT75L03D r egister m ap - q uick l ook a ddress l ocation r egister n ame b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 57 0x04 cr4 r/w transmit control register - channel 0 0x05 cr5 r/w receive control register - channel 0 0x06 cr6 r/w channel control register - channel 0 0x07 cr7 r/w jitter attenuator control register - channel 0 c hannel 1 c ontrol r egisters 0x08 cr8 r/o reserved 0x09 cr9 r/w source level interrupt enable register - channel 1 0x0a cr10 rur source level interrupt status register - channel 1 0x0b cr11 r/o alarm status register - channel 1 0x0c cr12 r/w transmit control register - channel 1 0x0d cr13 r/w receive control register - channel 1 0x0e cr14 r/w channel control register - channel 1 0x0f cr15 r/w jitter attenuator control register - channel 1 c hannel 2 c ontrol r egisters 0x10 cr16 r/w reserved 0x11 cr17 r/w source level interrupt enable register - channel 2 0x12 cr18 rur source level interrupt status register - channel 2 0x13 cr19 r/o alarm status register - channel 2 0x14 cr20 r/w transmit control register - channel 2 0x15 cr21 r/w receive control register - channel 2 0x16 cr22 r/w channel control register - channel 2 0x17 cr23 r/w jitter attenuator control register - channel 2 0x18 - 0x1f reserved b lock l evel i nterrupt e nable /s tatus r egisters (c hannels 0 - 2) 0x20 cr32 r/w block level interrupt enable register 0x21 cr33 r/o block level interrupt status register 0x22 - 0x3d reserved reserved d evice i dentification r egisters 0x3e cr62 r/o device part number register 0x3f cr63 r/o chip revision number register t able 16: c ommand r egister a ddress m ap , within the XRT75L03D 3-c hannel ds3/e3/sts-1 liu w / j itter a ttenuator ic a ddress c ommand r egister t ype r egister n ame
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 58 the global/chip-level registers the register set, within the XRT75L03D consists of five "global" or "chip-level" registers and 21 per-channel registers. this section will present detailed information on the global registers. register description - global registers t able 17: l ist and a ddress l ocations of g lobal r egisters a ddress c ommand r egister t ype r egister n ame 0x00 cr0 r/w aps/redundancy control register 0x01 - 0x1f bank of per-channel registers 0x20 cr32 r/w block level interrupt enable register 0x21 cr33 r/o block level interrupt status register 0x22 - 0x3d reserved registers 0x3e cr62 r/o device/part number register 0x3f cr63 r/o chip revision number register t able 18: aps/r edundancy c ontrol r egister - cr0 (a ddress l ocation = 0 x 00) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved rxonch 2 rxon ch 1 rxon ch 0 reserved txon ch 2 txon ch 1 txon ch 0 r/o r/w r/w r/w r/o r/w r/w r/w 00000000 b it n umber n ame t ype d efault v alue d escription 7 reserved r/o 0 6 rxon ch 2 r/w 0 receiver section on - channel 2 this read/write bit-field is used to either turn on or turn off the receive section of channel 2. if the user turns on the receive sec- tion, then channel 2 will begin to receive the incoming ds3, e3 or sts-1 data-stream via the rtip_2 and rring_2 input pins. conversely, if the user turns off the receive section, then the entire receive section (e.g., agc and receive equalizer block, clock recovery pll, etc) will be powered down. 0 - shuts off the receive section of channel 2. 1 - turns on the receive section of channel 2.
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 59 5 rxon ch 1 r/w 0 receiver section on - channel 1 this read/write bit-field is used to either turn on or turn off the receive section of channel 1. if the user turns on the receive sec- tion, then channel 1 will begin to receive the incoming ds3, e3 or sts-1 data-stream via the rtip_1 and rring_1 input pins. conversely, if the user turns off the receive section, then the entire receive section (e.g., agc and receive equalizer block, clock recovery pll, etc) will be powered down. 0 - shuts off the receive section of channel 1. 1 - turns on the receive section of channel 1. 4 rxon ch 0 r/w 0 receiver section on - channel 0 this read/write bit-field is used to either turn on or turn off the receive section of channel 0. if the user turns on the receive sec- tion, then channel 0 will begin to receive the incoming ds3, e3 or sts-1 data-stream via the rtip_0 and rring_0 input pins. conversely, if the user turns off the receive section, then the entire receive section (e.g., agc and receive equalizer block, clock recovery pll, etc) will be powered down. 0 - shuts off the receive section of channel 0. 1 - turns on the receive section of channel 0. 3 reserved r/o 0 2txon ch 2r/w0 transmit driver on - channel 2 this read/write bit-field is used to either turn on or turn off the transmit driver associated with channel 2. if the user turns on the transmit driver, then channel 2 will begin to transmit ds3, e3 or sts-1 pulses on the line via the ttip_2 and tring_ 2 output pins. conversely, if the user turns off the transmit driver, then the ttip_2 and tring_2 output pins will be tri-stated. 0 - shuts off the transmit driver associated with channel 2 and tri- states the ttip_2 and tring_ 2 output pins. 1 - turns on or enables the transmit driver associated with channel 2. n ote : if the user wishes to exercise software control over the state of the transmit driver associated with channel 2, then it is imperative that the user pull the txon_2 (pin 125) to a logic "high" level. b it n umber n ame t ype d efault v alue d escription
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 60 1txon ch 1r/w0 transmit section on - channel 1 this read/write bit-field is used to either turn on or turn off the transmit driver associated with channel 1. if the user turns on the transmit driver, then channel 1 will begin to transmit ds3, e3 or sts-1 pulses on the line via the ttip_1 and tring_ 1 output pins. conversely, if the user turns off the transmit driver, then the ttip_1 and tring_1 output pins will be tri-stated. 0 - shuts off the transmit driver associated with channel 1 and tri- states the ttip_1 and tring_ 1 output pins. 1 - turns on or enables the transmit driver associated with channel 1. n ote : if the user wishes to exercise software control over the state of the transmit driver associated with channel 1, then it is imperative that the user pull the txon_1 (pin 1) to a logic "high" level. 0txon ch 0r/w0 transmit section on - channel 0 this read/write bit-field is used to either turn on or turn off the transmit driver associated with channel 0. if the user turns on the transmit driver, then channel 0 will begin to transmit ds3, e3 or sts-1 pulses on the line via the ttip_0 and tring_ 0 output pins. conversely, if the user turns off the transmit driver, then the ttip_0 and tring_0 output pins will be tri-stated. 0 - shuts off the transmit driver associated with channel 0 and tri- states the ttip_0 and tring_ 0 output pins. 1 - turns on or enables the transmit driver associated with channel 0. n ote : if the user wishes to exercise software control over the state of the transmit driver associated with channel 0, then it is imperative that the user pull the txon_0 (pin 38) to a logic "high" level. b it n umber n ame t ype d efault v alue d escription
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 61 t able 19: b lock l evel i nterrupt e nable r egister - cr32 (a ddress l ocation = 0 x 20) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved channel 2 interrupt enable channel 1 interrupt enable channel 0 interrupt enable r/o r/o r/o r/o r/o r/w r/w r/w 00000000 b it n umber n ame t ype d efault v alue d escription 7 - 3 unused r/o 0 2 channel 2 inter- rupt enable r/w 0 channel 2 interrupt enable bit: this read/write bit-field is used to do either of the following ? to enable channel 2 for interrupt generation at the block level ? to disable all interrupts associated with channel 2 within the XRT75L03D if the user enables channel 2-related interrupts at the block level, then this means that a given channel 2-related interrupt (e.g., change in los defect condition - channel 2) will be enabled if the user has also enabled this particular interrupt at the source level. if the user disables channel 2-related interrupts at the block level, then this means that the XRT75L03D will not generate any channel 2-related interrupts at all. 0 - disables all channel 2-related interrupt. 1 - enables channel 2-related interrupts at the block level. the user must still enable individual channel 2-related interrupts at the source level, before they are enabled for interrupt generation. 1 channel 1 inter- rupt enable r/w 0 channel 1 interrupt enable bit: please see the description for bit 2 channel 2 interrupt enable. 0 channel 0 inter- rupt enable r/w 0 channel 0 interrupt enable bit: please see the description for bit 2 channel 2 interrupt enable.
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 62 t able 20: b lock l evel i nterrupt s tatus r egister - cr33 (a ddress l ocation = 0 x 21) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 reserved channel 2 interrupt status channel 1 interrupt status channel 0 interrupt status r/o r/o r/o r/o r/o r/o r/o r/o 00000 0 0 0 b it n umber n ame t ype d efault v alue d escription 7 - 3 unused r/o 0 2 channel 2 inter- rupt sta- tus r/o 0 channel 2 interrupt status bit: this read-only bit-field indicates whether or not the XRT75L03D has a pending channel 2-related interrupt that is awaiting service. 0 - indicates that there is no channel 2-related interrupt awaiting service. 1 - indicates that there is at least one channel 2-related interrupt awaiting service. in this case, the user's interrupt service routine should be written such that the microprocessor will now proceed to read out the contents of the source level interrupt status register - channel 2 (address location = 0x12) in order to determine the exact cause of the interrupt request. n ote : once this bit-field is set to "1", it will not be cleared back to "0" until the user has read out the contents of the source- level interrupt status register bit, that corresponds with the interrupt request.
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 63 1 channel 1 inter- rupt enable r/w 0 channel 1 interrupt enable bit: this read-only bit-field indicates whether or not the XRT75L03D has a pending channel 1-related interrupt that is awaiting service. 0 - indicates that there is no channel 1-related interrupt awaiting service. 1 - indicates that there is at least one channel 1-related interrupt awaiting service. in this case, the user's interrupt service routine should be written such that the microprocessor will now proceed to read out the contents of the source level interrupt status register - channel 1 (address location = 0x0a) in order to determine the exact cause of the interrupt request. n ote : once this bit-field is set to "1", it will not be cleared back to "0" until the user has read out the contents of the source- level interrupt status register bit, that corresponds with the interrupt request. 0 channel 0 inter- rupt enable r/w 0 channel 0 interrupt enable bit: this read-only bit-field indicates whether or not the XRT75L03D has a pending channel 0-related interrupt that is awaiting service. 0 - indicates that there is no channel 0-related interrupt awaiting service. 1 - indicates that there is at least one channel 0-related interrupt awaiting service. in this case, the user's interrupt service routine should be written such that the microprocessor will now proceed to read out the contents of the source level interrupt status register - channel 0 (address location = 0x02) in order to determine the exact cause of the interrupt request. n ote : once this bit-field is set to "1", it will not be cleared back to "0" until the user has read out the contents of the source- level interrupt status register bit, that corresponds with the interrupt request. t able 21: d evice /p art n umber r egister - cr62 (a ddress l ocation = 0 x 3e) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 part number id value r/o r/o r/o r/o r/o r/o r/o r/o 01110011 b it n umber n ame t ype d efault v alue d escription 7 - 0 part number id value r/o 0x73 part number id value: this read-only register contains a unique value that represents the XRT75L03D. b it n umber n ame t ype d efault v alue d escription
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 64 the per-channel registers the XRT75L03D consists of 21 per-channel registers. table 23 presents the overall register map with the per-channel registers shaded. t able 22: c hip r evision n umber r egister - cr63 (a ddress l ocation = 0 x 3f) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 chip revision number value r/o r/o r/o r/o r/o r/o r/o r/o 0 0 0 0xxxx b it n umber n ame t ype d efault v alue d escription 7 - 0 chip revision number value r/o 0x0# chip revision number value: this read-only register contains a value that represents the current revision of this XRT75L03D. this revision num- ber will always be in the form of "0x0#", where "#" is a hexadecimal value that specifies the current revision of the chip. for example, the very first revision of this chip will contain the value "0x01". t able 23: c ommand r egister a ddress m ap , within the XRT75L03D 3-c hannel ds3/e3/sts-1 liu w / j itter a ttenuator ic a ddress c ommand r egister t ype r egister n ame 0x00 cr0 r/w aps/redundancy control register c hannel 0 c ontrol r egisters 0x01 cr1 r/o source level interrupt enable register - channel 0 0x02 cr2 r/w source level interrupt status register channel 0 0x03 cr3 r/o alarm status register - channel 0 0x04 cr4 r/w transmit control register - channel 0 0x05 cr5 r/w receive control register - channel 0 0x06 cr6 r/w channel control register - channel 0 0x07 cr7 r/w jitter attenuator control register - channel 0 c hannel 1 c ontrol r egisters 0x08 cr8 r/o reserved 0x09 cr9 r/w source level interrupt enable register - channel 1 0x0a cr10 rur source level interrupt status register - channel 1 0x0b cr11 r/o alarm status register - channel 1 0x0c cr12 r/w transmit control register - channel 1
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 65 0x0d cr13 r/w receive control register - channel 1 0x0e cr14 r/w channel control register - channel 1 0x0f cr15 r/w jitter attenuator control register - channel 1 c hannel 2 c ontrol r egisters 0x10 cr16 r/w reserved 0x11 cr17 r/w source level interrupt enable register - channel 2 0x12 cr18 rur source level interrupt status register - channel 2 0x13 cr19 r/o alarm status register - channel 2 0x14 cr20 r/w transmit control register - channel 2 0x15 cr21 r/w receive control register - channel 2 0x16 cr22 r/w channel control register - channel 2 0x17 cr23 r/w jitter attenuator control register - channel 2 0x18 - 0x1f reserved b lock l evel i nterrupt e nable /s tatus r egisters (c hannels 0 - 2) 0x20 cr32 r/w block level interrupt enable register 0x21 cr33 r/o block level interrupt status register 0x22 - 0x3d reserved reserved d evice i dentification r egisters 0x3e cr62 r/o device part number register 0x3f cr63 r/o chip revision number register t able 23: c ommand r egister a ddress m ap , within the XRT75L03D 3-c hannel ds3/e3/sts-1 liu w / j itter a ttenuator ic a ddress c ommand r egister t ype r egister n ame
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 66 register description - per channel registers t able 24: s ource l evel i nterrupt e nable r egister - c hannel 0 a ddress l ocation = 0 x 01 channel 1 address location = 0x09 channel 2 address location = 0x11 ) b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused change of fl condition interrupt enable ch 0 change of lol condition interrupt enable ch 0 change of los condition interrupt enable ch 0 change of dmo condition interrupt enable ch 0 r/o r/o r/o r/o r/w r/w r/w r/w 0000 0 0 0 0 b it n umber n ame t ype d efault v alue d escription 7 - 4 reserved r/o 0 3 change of fl condition interrupt enable - ch 0 r/w 0 change of fl (fifo limit alarm) condition interrupt enable - ch 0: this read/write bit-field is used to either enable or dis- able the change of fl condition interrupt. if the user enables this interrupt, then the XRT75L03D will generate an interrupt any time any of the following events occur. ? whenever the jitter attenuator (within channel 0) declares the fl (fifo limit alarm) condition. ? whenever the jitter attenuator (within channel 0) clears the fl (fifo limit alarm) condition. 0 - disables the change in fl condition interrupt. 1 - enables the change in fl condition interrupt. 2 change of lol condition interrupt enable r/w 0 change of receive lol (loss of lock) condition inter- rupt enable - channel 0: this read/write bit-field is used to either enable or dis- able the change of receive lol condition interrupt. if the user enables this interrupt, then the XRT75L03D will gen- erate an interrupt any time any of the following events occur. ? whenever the receive section (within channel 0) declares the loss of lock condition. ? whenever the receive section (within channel 0) clears the loss of lock condition. 0 - disables the change in receive lol condition inter- rupt. 1 - enables the change in receive lol condition inter- rupt.
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 67 1 change of los condition interrupt enable r/w 0 change of the receive los (loss of signal) defect condition interrupt enable - ch 0: this read/write bit-field is used to either enable or dis- able the change of the receive los defect condition interrupt. if the user enables this interrupt, then the XRT75L03D will generate an interrupt any time any of the following events occur. ? whenever the receive section (within channel 0) declares the los defect condition. ? whenever the receive section (within channel 0) clears the los defect condition. 0 - disables the change in the los defect condition inter- rupt. 1 - enables the change in the los defect condition inter- rupt. 0 change of dmo condition interrupt enable r/w 0 change of transmit dmo (drive monitor output) con- dition interrupt enable - ch 0: this read/write bit-field is used to either enable or dis- able the change of transmit dmo condition interrupt. if the user enables this interrupt, then the XRT75L03D will generate an interrupt any time any of the following events occur. ? whenever the transmit section toggles the dmo output pin (or bit-field) to "1". ? whenever the transmit section toggles the dmo output pin (or bit-field) to "0". 0 - disables the change in the dmo condition interrupt. 1 - enables the change in the dmo condition interrupt. b it n umber n ame t ype d efault v alue d escription
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 68 t able 25: s ource l evel i nterrupt s tatus r egister - c hannel 0 a ddress l ocation = 0 x 02 channel 1 address location = 0x0a channel 2 address location = 0x12 b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused change of fl condition interrupt status ch_n change of lol condition interrupt status ch_n change of los condition nterrupt status ch_n change of dmo condition interrupt status ch_n r/o r/o r/o r/o rur rur rur rur 0000 0 0 0 0 b it n umber n ame t ype d efault v alue d escription 7 - 4 unused r/o 0 3 change of fl con- dition interrupt sta- tus rur 0 change of fl (fifo limit alarm) condition interrupt status - ch 0: this reset-upon-read bit-field indicates whether or not the change of fl condition interrupt (for channel 0) has occurred since the last read of this register. 0 - indicates that the change of fl condition interrupt has not occurred since the last read of this register. 1 - indicates that the change of fl condition interrupt has occurred since the last read of this register. n ote : the user can determine the current state of the fifo alarm condition by reading out the contents of bit 3 (fl alarm declared) within the alarm status register. 2 change of lol condition interrupt status rur 0 change of receive lol (loss of lock) condition inter- rupt status - ch 0: this reset-upon-read bit-field indicates whether or not the change of receive lol condition interrupt (for chan- nel 0) has occurred since the last read of this register. 0 - indicates that the change of receive lol condition interrupt has not occurred since the last read of this reg- ister. 1 - indicates that the change of receive lol condition interrupt has occurred since the last read of this register. n ote : the user can determine the current state of the receive lol defect condition by reading out the contents of bit 2 (receive lol defect declared) within the alarm status register.
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 69 1 change of los condition interrupt status rur 0 change of receive los (loss of signal) defect condi- tion interrupt status: this reset-upon-read bit-field indicates whether or not the change of the receive los defect condition interrupt (for channel 0) has occurred since the last read of this reg- ister. 0 - indicates that the change of the receive los defect condition interrupt has not occurred since the last read of this register. 1 - indicates that the change of the receive los defect condition interrupt has occurred since the last read of this register. n ote : the user can determine the current state of the receive los defect condition by reading out the contents of bit 1 (receive los defect declared) within the alarm status register. 0 change of dmo condition interrupt status rur 0 change of transmit dmo (drive monitor output) con- dition interrupt status - ch 0: this reset-upon-read bit-field indicates whether or not the change of the transmit dmo condition interrupt (for channel 0) has occurred since the last read of this register. 0 - indicates that the change of the transmit dmo condi- tion interrupt has not occurred since the last read of this register. 1 - indicates that the change of the transmit dmo condi- tion interrupt has occurred since the last read of this regis- ter. n ote : the user can determine the current state of the transmit dmo condition by reading out the contents of bit 0 (transmit dmo condition) within the alarm status register. b it n umber n ame t ype d efault v alue d escription
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 70 t able 26: a larm s tatus r egister - c hannel 0 a ddress l ocation = 0 x 03 channel 1 address location = 0x0b channel 2 address location = 0x13 b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused loss of prbs pattern sync digital los defect declared analog los defect declared fl (fifo limit) alarm declared receive lol defect declared receive los defect declared transmit dmo condition r/o r/o r/o r/o r/o r/o r/o r/o 00000000 b it n umber n ame t ype d efault v alue d escription 7unusedr/o0 6 loss of prbs pat- tern lock r/o 0 loss of prbs pattern lock indicator: this read-only bit-field indicates whether or not the prbs receiver (within the receive section of channel 0) is declaring prbs lock within the incoming prbs pattern. if the prbs receiver detects a very large number of bit- errors within its incoming data-stream, then it will declare the loss of prbs lock condition. conversely, if the prbs receiver were to detect its pre- determined prbs pattern with the incoming ds3, e3 or sts-1 data-stream, (with little or no bit errors) then the prbs receiver will clear the loss of prbs lock condition. 0 - indicates that the prbs receiver is currently declaring the prbs lock condition within the incoming ds3, e3 or sts-1 data-stream. 1 - indicates that the prbs receiver is currently declaring the loss of prbs lock condition within the incoming ds3, e3 or sts-1 data-stream. n ote : this register bit is only valid if all of the following are true. a. the prbs generator block (within the transmit section of the chip is enabled). b. the prbs receiver is enabled. c. the prbs pattern (that is generated by the prbs generator) is somehow looped back into the receive path (via the line-side) and in-turn routed to the receive input of the prbs receiver.
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 71 5 digital los defect declared r/o 0 digital los defect declared: this read-only bit-field indicates whether or not the dig- ital los (loss of signal) detector is declaring the los defect condition. for ds3 and sts-1 applications, the digital los detector will declare the los defect condition whenever it detects an absence of pulses (within the incoming ds3 or sts-1 data-stream) for 160 consecutive bit-periods. further, (again for ds3 and sts-1 applications) the digital los detector will clear the los defect condition whenever it determines that the pulse density (within the incoming ds3 or sts-1 signal) is at least 33%. 0 - indicates that the digital los detector is not declaring the los defect condition. 1 - indicates that the digital los detector is currently declaring the los defect condition. n otes : 1. los detection (within each channel of the XRT75L03D) is performed by both an analog los detector and a digital los detector. the los state of a given channel is simply a wired- or of the los defect declare states of these two detectors. 2. the current los defect condition (for the channel) can be determined by reading out the contents of bit 1 (receive los defect declared) within this register. b it n umber n ame t ype d efault v alue d escription
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 72 4 analog los defect declared r/o 0 analog los defect declared: this read-only bit-field indicates whether or not the analog los (loss of signal) detector is declaring the los defect condition. for ds3 and sts-1 applications, the analog los detector will declare the los defect condition whenever it deter- mines that the amplitude of the pulses (within the incoming ds3/sts-1 line signal) drops below a certain analog los defect declaration threshold level. conversely, (again for ds3 and sts-1 applications) the analog los detector will clear the los defect condition whenever it determines that the amplitude of the pulses (within the incoming ds3/sts-1 line signal) has risen above a certain analog los defect clearance threshold level. it should be noted that, in order to prevent "chattering" within the analog los detector output, there is some built- in hysteresis between the analog los defect declaration and the analog los defect clearance threshold levels. 0 - indicates that the analog los detector is not declar- ing the los defect condition. 1 - indicates that the analog los detector is currently declaring the los defect condition. n otes : 1. los detection (within each channel of the XRT75L03D) is performed by both an analog los detector and a digital los detector. the los state of a given channel is simply a wired- or of the los defect declare states of these two detectors. 2. the current los defect condition (for the channel) can be determined by reading out the contents of bit 1 (receive los defect declared) within this register. b it n umber n ame t ype d efault v alue d escription
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 73 3 fl alarm declared r/o 0 fl (fifo limit) alarm declared: this read-only bit-field indicates whether or not the jit- ter attenuator block (within channel_n) is currently declar- ing the fifo limit alarm. the jitter attenuator block will declare the fifo limit alarm anytime the jitter attenuator fifo comes within two bit-periods of either overflowing or under-running. conversely, the jitter attenuator block will clear the fifo limit alarm anytime the jitter attenuator fifo is no longer within two bit-periods of either overflowing or under- running. typically, this alarm will only be declared whenever there is a very serious problem with timing or jitter in the system. 0 - indicates that the jitter attenuator block (within channel_n) is not currently declaring the fifo limit alarm condition. 1 - indicates that the jitter attenuator block (within channel_n) is currently declaring the fifo limit alarm condition. n ote : this bit-field is only active if the jitter attenuator (within channel_n) has been enabled. 2 receive lol con- dition declared r/o 0 receive lol (loss of lock) condition declared: this read-only bit-field indicates whether or not the receive section (within channel_n) is currently declaring the lol (loss of lock) condition. the receive section (of channel_n) will declare the lol condition, if any one of the following conditions are met. ? if the frequency of the recovered clock signal differs from that of the signal provided to the e3clk input (for e3 applications), the ds3clk input (for ds3 applications) or the sts-1clk input (for sts-1 applications) by 0.5% (or 5000ppm) or more. ? if the frequency of the recovered clock signal differs from the line-rate clock signal (for channel_n) that has been generated by the sfm clock synthesizer pll (for sfm mode operation) by 0.5% (or 5000ppm) or more. 0 - indicates that the receive section of channel_n is not currently declaring the lol condition. 1 - indicates that the receive section of channel_n is cur- rently declaring the lol condition. b it n umber n ame t ype d efault v alue d escription
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 74 1 receive los defect condition declared r/o 0 receive los (loss of signal) defect condition declared: this read-only bit-field indicates whether or not the receive section (within channel_n) is currently declaring the los defect condition. the receive section (of channel_n) will declare the los defect condition, if any one of the following conditions is met. ? if the digital los detector declares the los defect condition (for ds3 or sts-1 applications) ? if the analog los detector declares the los defect condition (for ds3 or sts-1 applications) ? if the itu-t g.775 los detector declares the los defect condition (for e3 applications). 0 - indicates that the receive section of channel_n is not currently declaring the los defect condition. 1 - indicates that the receive section of channel_n is cur- rently declaring the los defect condition. 0transmit dmo condition declared r/o 0 transmit dmo (drive monitor output) condition declared: this read-only bit-field indicates whether or not the transmit section of channel_n is currently declaring the dmo alarm condition. if configured accordingly, the transmit section will either internally or externally check the transmit output ds3/e3/ sts-1 line signal for bipolar pulses via the ttip_n and tring_n output signals. if the transmit section were to detect no bipolar for 128 consecutive bit-periods, then it will declare the transmit dmo alarm condition. this par- ticular alarm can be used to check for fault conditions on the transmit output line signal path. the transmit section will clear the transmit dmo alarm condition the instant that it detects some bipolar activity on the transmit output line signal. 0 - indicates that the transmit section of channel_n is not currently declaring the transmit dmo alarm condi- tion. 1 - indicates that the transmit section of channel_n is cur- rently declaring the transmit dmo alarm condition. b it n umber n ame t ype d efault v alue d escription
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 75 t able 27: t ransmit c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 04 channel 1 address location = 0x0c channel 2 address location = 0x14 b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused internal tr a n s m i t drive monitor insert prbs error unused taos txclkinv txlev r/o r/o r/w r/w r/o r/w r/w r/w 00000000 b it n umber n ame t ype d efault v alue d escription 7 - 6 unused r/o 0 5 internal transmit drive monitor r/w 0 internal transmit drive monitor enable - channel_n: this read/write bit-field is used to configure the trans- mit section of channel_n to either internally or externally monitor the ttip_n and tring_n output pins for bipolar pulses, in order to determine whether to declare the trans- mit dmo alarm condition. if the user configures the transmit section to externally monitor the ttip_n and tring_n output pins (for bipolar pulses) then the user must make sure that he/she has con- nected the mtip_n and mring_n input pins to their corre- sponding ttip_n and tring_n output pins (via a 274 ohm series resistor). if the user configures the transmit section to internally monitor the ttip_n and tring_n output pins (for bipolar pulses) then the user does not need to make sure that the mtip_n and mring_n input pins are connected to the ttip_n and tring_n output pins (via series resistors). this monitoring will be performed right at the ttip_n and tring_n output pads. 0 - configures the transmit drive monitor to externally monitor the ttip_n and tring_n output pins for bipolar pulses. 1 - configures the transmit drive monitor to internally monitor the ttip_n and tring_n output pins for bipolar pulses.
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 76 4 insert prbs error r/w 0 insert prbs error - channel_n: a "0 to 1" transition within this bit-field configures the prbs generator (within the transmit section of channel_n) to generate a single bit error within the out- bound prbs pattern-stream. n otes : 1. this bit-field is only active if the prbs generator and receiver have been enabled within the corresponding channel. 2. after writing the "1" into this register, the user must execute a write operation to clear this particular register bit to "0" in order to facilitate the next "0 to 1" transition in this bit-field. 3unusedr/o0 2taos r/w0 transmit all ones pattern - channel_n: this read/write bit-field is used to command the trans- mit section of channel_n to generate and transmit an unframed, all ones pattern via the ds3, e3 or sts-1 line signal (to the remote terminal equipment). whenever the user implements this configuration setting then the transmit section will ignore the data that it is accepting from the system-side equipment and overwrite this data with the "all ones" pattern. 0 - configures the transmit section to transmit the data that it accepts from the system-side interface. 1 - configures the transmit section to generate and trans- mit the unframed, all ones pattern. b it n umber n ame t ype d efault v alue d escription
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 77 1 txclkinv r/w 0 transmit clock invert select - channel_n: this read/write bit-field is used to select the edge of the txclk_n input that the transmit section of channel_n will use to sample the tpdata_n and tndata_n input pins, as described below. 0 - configures the transmit section (within the correspond- ing channel) to sample the tpdata_n and tndata_n input pins upon the falling edge of txclk_n. 1 - configures the transmit section (within the correspond- ing channel) to sample the tpdata_n and tndata_n input pins upon the rising edge of txclk_n. n ote : whenever this configuration setting is accomplished via the host mode, it is done on a per-channel basis. 0txlevr/w0 transmit line build-out select - channel_n: this read/write bit-field is used to either enable or dis- able the transmit line build-out (e.g., pulse-shaping) cir- cuit within the corresponding channel. the user should set this bit-field to either "0" or to "1" based upon the following guidelines. 0 - if the cable length between the transmit output (of the corresponding channel) and the dsx-3/stsx-1 location is 225 feet or less. 1 - if the cable length between the transmit output (of the corresponding channel) and the dsx-3/stsx-1 location is 225 feet or more. the user must follow these guidelines in order to insure that the transmit section (of channel_n) will always gener- ate a ds3 pulse that complies with the isolated pulse tem- plate requirements per bellcore gr-499-core, or an sts-1 pulse that complies with the pulse template requirements per telcordia gr-253-core. n ote : this bit-field is ignored if the channel has been configured to operate in the e3 mode. b it n umber n ame t ype d efault v alue d escription
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 78 t able 28: r eceive c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 05 channel 1 address location = 0x0d channel 2 address location = 0x15 b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused disable dlos detector disable alos detector rxclkinv losmut enable receive monitor mode enable receive equalizer enable r/o r/o r/w r/w r/w r/w r/w r/w 00000000 b it n umber n ame t ype d efault v alue d escription 7 - 6 unused r/o 0 5 disable dlos detector r/w 0 disable digital los detector - channel_n: this read/write bit-field is used to either enable or dis- able the digital los (loss of signal) detector within channel_n, as described below. 0 - enables the digital los detector within channel_n. n ote : this is the default condition. 1 - disables the digital los detector within channel_n. n ote : this bit-field is only active if channel_n has been configured to operate in the ds3 or sts-1 modes. 4 disable alos detector r/w 0 disable analog los detector - channel_n: this read/write bit-field is used to either enable or dis- able the analog los (loss of signal) detector within channel_n, as described below. 0 - enables the analog los detector within channel_n. n ote : this is the default condition. 1 - disables the analog los detector within channel_n. n ote : this bit-field is only active if channel_n has been configured to operate in the ds3 or sts-1 modes. 3 rxclkinv r/w 0 receive clock invert select - channel_n: this read/write bit-field is used to select the edge of the rclk_n output that the receive section of channel_n will use to output the recovered data via the rpos_n and rneg_n output pins, as described below. 0 - configures the receive section (within the correspond- ing channel) to output the recovered data via the rpos_n and rneg_n output pins upon the rising edge of rclk_n. 1 - configures the receive section (within the correspond- ing channel) to output the recovered data via the rpos_n and rneg_n output pins upon the falling edge of rclk_n.
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 79 2losmut enabler/w 0 muting upon los enable - channel_n: this read/write bit-field is used to configure the receive section (within channel_n) to automatically pull their corresponding recovered data output pins (e.g., rpos_n and rneg_n) to gnd anytime (and for the dura- tion that) the receive section declares the los defect condition. in other words, this feature (if enabled) will cause the receive channel to automatically mute the recovered data anytime (and for the duration that) the receive section declares the los defect condition. 0 - disables the muting upon los feature. in this setting the receive section will not automatically mute the recovered data whenever it is declaring the los defect condition. 1 - enables the muting upon los feature. in this setting the receive section will automatically mute the recovered data whenever it is declaring the los defect condition. 1 receive monitor mode enable r/w 0 receive monitor mode enable - channel_n: this read/write bit-field is used to configure the receive section of channel_n to operate in the receive monitor mode. if the user configures the receive section to operate in the receive monitor mode, then it will be able to receive a nominal dsx-3/stsx-1 signal that has been attenuator by 20db of flat loss along with 6db of cable loss, in an error- free manner, and without declaring the los defect condi- tion. 0 - configures the corresponding channel to operate in the normal mode. 1 - configure the corresponding channel to operate in the receive monitor mode. 0 receive equalizer enable r/w 0 receive equalizer enable - channel_n: this read/write register bit is used to either enable or disable the receive equalizer block within the receive section of channel_n, as listed below. 0 - disables the receive equalizer within the correspond- ing channel. 1 - enables the receive equalizer within the corresponding channel. n ote : for virtually all applications, we recommend that the user set this bit-field to "1" (for all three channels) and enable the receive equalizer. b it n umber n ame t ype d efault v alue d escription
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 80 t able 29: c hannel c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 06 channel 1 address location = 0x0e channel 2 address location = 0x16 b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused prbs enable ch_n rlb_n llb_n e3_n sts-1/ds3 _n sr/dr _n r/o r/o r/w r/w r/w r/w r/w r/w 00000000 b it n umber n ame t ype d efault v alue d escription 7 - 6 unused r/o 0 5 prbs enable r/w 0 prbs generator and receiver enable - channel_n: this read/write bit-field is used to either enable or dis- able the prbs generator and receiver within a given channel of the XRT75L03D. if the user enables the prbs generator and receiver, then the following will happen. 1. the prbs generator (which resides within the transmit section of the channel) will begin to generate an unframed, 2^15-1 prbs pattern (for ds3 and sts-1 applications) and an unframed, 2^23-1 prbs pattern (for e3 applications). 2. the prbs receiver (which resides within the receive section of the channel) will now be enabled and will begin to search the incoming data for the above-mentioned prbs patterns. 0 - disables both the prbs generator and prbs receiver within the corresponding channel. 1 - enables both the prbs generator and prbs receiver within the corresponding channel. n otes : 1. to check and monitor prbs bit errors, bit 0 (sr/ dr _n) within this register must be set to "0". this step will configure the rneg_n/lcv_n output pin to function as the prbs error indicator. in this case, external glue logic will be needed to monitor and count the number of prbs bit errors that are detected by the prbs receiver. 2. if the user enables the prbs generator and prbs receiver, then the channel will ignore the data that is being accepted from the system-side equipment (via the tpdata_n and tndata_n input pins) and will overwrite this outbound data with the prbs pattern. 3. use of the prbs generator and receiver is only available through the host mode.
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 81 4rlb_nr/w0 loop-back select - rlb bit - channel_n: this read/write bit-field along with the corresponding llb_n bit-field is used to configure a given channel (within the XRT75L03D) into various loop-back modes. the relationship between the settings for this input pin, the corresponding llb_n bit-field and the resulting loop-back mode is presented below. 3 llb_n r/w 0 loop-back select - llb bit-field - channel_n: please see the description (above) for rlb_n. 2e3_nr/w0 e3 mode select - channel_n: this read/write bit-field, along with bit 1 (sts-1/ ds3 _n) within this particular register, is used to configure a given channel (of the XRT75L03D) into either the ds3, e3 or sts-1 modes, as depicted below. 0 - configures channel_n to operate in either the ds3 or sts-1 modes, depending upon the state of bit 1 (sts-1/ ds3 _n) within this same register. 1- configures channel_n to operate in the e3 mode. b it n umber n ame t ype d efault v alue d escription loop-back mode digital local loop-back mode analog local loop-back mode remote loop-back mode normal (no loop-back) mode rlb_n 1 0 1 0 llb_n 1 1 0 0
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 82 1 sts-1/ ds3 _n r/w 0 sts-1/ds3 mode select - channel_n: this read/write bit-field, along with bit 2 (e3_n) is used to configure a given channel (within the XRT75L03D) into either the ds3, e3 or sts-1 modes. 0 - configures channel_n to operate in the ds3 mode (provided by bit 2 [e3_n], within this same register) has been set to "0"). 1 - configures channel_n to operate in the sts-1 mode (provided that bit 2 [e3_n], within the same register) has been set to "0". n ote : this bit-field is ignored if bit 2 (e3_n) has been set to "1". in this case, channel_n will be configured to operate in the e3 mode. 0 sr/dr _n r/w 0 single-rail/dual-rail select - channel_n: this read/write bit-field is used to configure channel_n to operate in either the single-rail or dual-rail mode. if the user configures the channel to operate in the single- rail mode, then all of the following will happen. ? the b3zs/hdb3 encoder and decoder blocks (within channel_n) will be enabled. ? the transmit section of channel_n will accept all of the outbound data (from the system-side equipment) via the tpdata_n (or txdata_n) input pin. ? the receive section of each channel will output all of the recovered data (to the system-side equipment) via the rpos_n output pin. ? the corresponding rneg_n/lcv_n output pin will now function as the lcv (line code violation or excessive zero event) indicator output pin for channel_n. if the user configures channel_n to operate in the dual- rail mode, then all of the following will happen. ? the b3zs/hdb3 encoder and decoder blocks of channel_n will be disabled. ? the transmit section of channel_n will be configured to accept positive-polarity data via the tpdata_n input pin and negative-polarity data via the tndata_n input pin. ? the receive section of channel_n will pulse the rpos_n output pin "high" (for one period of rclk_n) for each time a positive-polarity pulse is received via the rtip_n/rring_n input pins. likewise, the receive section of each channel will also pulse the rneg_n output pin "high" (for one period of rclk_n) for each time a negative-polarity pulse is received via the rtip_n/rring_n input pins. 0 - configures channel_n to operate in the dual-rail mode. 1 - configures channel_n to operate in the single-rail mode. b it n umber n ame t ype d efault v alue d escription
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 83 t able 30: j itter a ttenuator c ontrol r egister - c hannel 0 a ddress l ocation = 0 x 07 channel 1 address location = 0x0f channel 2 address location = 0x17 b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 unused sonet aps recovery time disable ch_n ja reset ch_n ja1 ch_n ja in tx path ch_n ja0 ch_n r/o r/o r/o r/w r/w r/w r/w r/w 00000000 b it n umber n ame t ype d efault v alue d escription 7 - 3 unused r/o 0 4 sonet aps recovery time mode disable ch_n r/w o sonet aps recovery time mode disable - channel n: this read/write bit-field is used to either enable or dis- able the "sonet aps recovery time" mode within the jit- ter attenuator, associated with channel n. if this feature is enabled the jitter attenuator (associated with channel n) will be configured such that the user's sys- tem will be able to comply with the aps recovery time requirements of 50ms (per telcordia gr-253-core). if this feature is disabled the system using the XRT75L03D will not comply with the aps recovery time require- ments of 50ms. n ote : in this case, "aps recovery time" is defined as the amount of time that will elapse between (a) the instant that automatic protection switching (aps) is employed (either "automatically" or upon software command), and (b) the instant that an entity (which is responsible for acquiring and maintaining ds3/e3 frame synchronization with the ds3/e3 data-stream that has been de-mapped from sonet by the mapper device) has re- acquired ds3/e3 frame synchronization, after the aps event. 0 - enables the "sonet aps recovery time" mode. 1 - disables the "sonet aps recovery time" mode.
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 84 3 ja reset ch_n r/w 0 jitter attenuator reset - channel_n: writing a "0 to 1" transition within this bit-field will configure the jitter attenuator (within channel_n) to execute a reset operation. whenever the user executes a reset operation, then all of the following will occur. ? the read and write pointers (within the jitter attenuator fifo) will be reset to their default values. ? the contents of the jitter attenuator fifo will be flushed. n ote : the user must follow up any "0 to 1" transition with the appropriate write operate to set this bit-field back to "0", in order to resume normal operation with the jitter attenuator. 2 ja1 ch_n r/w 0 jitter attenuator configuration select input - bit 1: this read/write bit-field, along with bit 0 (ja0 ch_n) is used to do any of the following. ? to enable or disable the jitter attenuator corresponding to channel_n. ? to select the fifo depth for the jitter attenuator within channel_n. the relationship between the settings of these two bit- fields and the enable/disable states, and fifo depths is presented below. 1 ja in tx path ch_n r/w 0 jitter attenuator in transmit/receive path select bit: this input pin is used to configure the jitter attenuator (within channel_n) to operate in either the transmit or receive path, as described below. 0 - configures the jitter attenuator (within channel_n) to operate in the receive path. 1 - configures the jitter attenuator (within channel_n) to operate in the transmit path. 0 ja0 ch_n r/w 0 jitter attenuator configuration select input - bit 0: please see the description for bit 2 (ja1 ch_n). b it n umber n ame t ype d efault v alue d escription ja0 ja1 jitter attenuator mode 1 1 jitter attenuator disabled 1 0 sonet/sdh de-sync mode 0 1 fifo depth = 32 bits 0 0 fifo depth = 16 bits
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 85 8.0 diagnostic features: 8.1 prbs generator and detector: the XRT75L03D contains an on-chip pseudo random binary sequence (prbs) generator and detector for diagnostic purpose. this feature is only available in host mode. with the prbsen_n bit = 1, the transmitter will send out prbs of 2 23 -1 in e3 rate or 2 15 -1 in sts-1/ds3 rate. at the same time, the receiver prbs detector is also enabled. when the correct prbs pattern is detected by the receiver, the rneg/lcv pin will go low to indicate prbs synchronization has been achieved. when the prbs detector is not in sync the prbsls bit will be set to 1 and rneg/lcv pin will go high. with the prbs mode enabled, the user can also insert a single bit error by toggling insprbs bit. this is done by writing a 1 to insprbs bit. the receiver at rneg/lcv pin will pulse high for one rxclk cycle for every bit error detected. any subsequent single bit error insertion must be done by first writing a 0 to insprbs bit and followed by a 1. figure 25 shows the status of rneg/lcv pin when the XRT75L03D is configured in prbs mode. n ote : in prbs mode, the device is forced to operate in single-rail mode. 8.2 loopbacks: the XRT75L03D offers three loopback modes for diagnostic purposes. in hardware mode, the loopback modes are selected via the rlb_n and llb_n pins. in host mode, the rlb_n and llb_n bits n the channel control registers select the loopback modes. 8.2.1 analog loopback: in this mode, the transmitter outputs (ttip_n and tring_n) are connected internally to the receiver inputs (rtip_n and rring_n) as shown in figure 26. data and clock are output at rclk_n, rpos_n and rneg_n pins for the corresponding transceiver. analog loopback exercises most of the functional blocks of the device including the jitter attenuator which can be selected in either the transmit or receive path. XRT75L03D can be configured in analog loopback either in hardware mode via the llb_n and rlb_n pins or in host mode via llb_n and rlb_n bits in the channel control registers. n otes : 1. in the analog loopback mode, data is also output via ttip_n and tring_n pins. 2. signals on the rtip_n and rring_n pins are ignored during analog loopback. f igure 25. prbs mode rclk rneg/lcv sync loss prbs sync single bit error
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 86 f igure 26. a nalog l oopback tring ttip rring rtip rpos rneg rclk tndata tclk tpdata hdb3/b3zs encoder hdb3/b3zs decoder jitter 2 attenuator jitter 2 attenuator timing control data & clock recovery 1 if enabled 2 if enabled and selected in either receive or transmit path tx rx 1 1
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 87 8.2.2 digital loopback: the digital loopback function is available either in hardware mode or host mode. when the digital loopback is selected, the transmit clock (txclk_n) and transmit data inputs (tpdata_n & tndata_n) are looped back and output onto the rxclk_n, rpos_n and rneg_n pins as shown in figure 27. 8.2.3 remote loopback: with remote loopback activated as shown in figure 28, the receive data on rtip and rring is looped back after the jitter attenuator (if selected in receive or transmit path) to the transmit path using rxclk as transmit timing. the receive data is also output via the rpos and rneg pins. during the remote loopback mode, if the jitter attenuator is selected in the transmit path, the receive data after the clock and data recovery block is looped back to the transmit path and passed through the jitter attenuator using rxclk as the transmit timing. n ote : input signals on txclk, tpdata and tndata are ignored during remote loopback. f igure 27. d igital l oopback f igure 28. r emote l oopback tring ttip rring rtip rpos rneg rclk tndata tclk tpdata hdb3/b3zs encoder hdb3/b3zs decoder jitter 2 attenuator jitter 2 attenuator timing control data & clock recovery 1 if enabled 2 if enabled and selected in either receive or transmit path tx rx 1 1 tring ttip rring rtip rpos rneg rclk tndata tclk tpdata hdb3/b3zs encoder hdb3/b3zs decoder jitter 2 attenuator jitter 2 attenuator timing control data & clock recovery 1 if enabled 2 if enabled and selected in either receive or transmit path tx rx 1 1
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 88 8.3 transmit all ones (taos): transmit all ones (taos) can be set either in hardware mode by pulling the taos_n pins high or in host mode by setting the taos_n control bits to 1 in the channel control registers. when the taos is set, the transmit section generates and transmits a continuous ami all 1s pattern on ttip_n and tring_n pins. the frequency of this 1s pattern is determined by tclk_n.taos data path is shown in figure 29. taos does not operate in analog loopback or remote digital loopback mode. it will function in digital loopback mode. f igure 29. t ransmit a ll o nes (taos) tring ttip rring rtip rpos rneg rclk tndata tclk tpdata hdb3/b3zs encoder hdb3/b3zs decoder jitter 2 attenuator jitter 2 attenuator timing control data & clock recovery 1 if enabled 2 if enabled and selected in either receive or transmit path tx rx taos transmit all 1 1 1
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 89 9.0 the sonet/sdh de-sync function within the XRT75L03D the XRT75L03D liu ic is very similar to the xrt75l03 in that they are both 3-channel ds3/e3/sts-1 liu devices that also contain jitter attenuator blocks within each of the three channels. they are also pin to pin compatible with each other. however, the jitter attenuators within the XRT75L03D has some enhancements over and above those within the xrt75l03 (non-d) device. the jitter attenuator blocks within the XRT75L03D will support all of the modes and features that exist in the xrt75l03 (non-d) device and in addition they also support a sonet/sdh de-sync mode not available within the XRT75L03D. n ote : the "d" suffix within the part number, XRT75L03D stands for "de-sync". the sonet/sdh de-sync feature of the jitter attenuator blocks in the XRT75L03D permits the user to design a sonet/sdh pte (path terminating equipment) that will comply with all of the following intrinsic jitter and wander requirements. for sonet applications n category i intrinsic jitter requirements per telcordia gr-253-core (for ds3 applications) n ansi t1.105.03b-1997 - sonet jitter at network interfaces - ds3 wander supplement for sdh applications n jitter and wander generation requirements per itu-t g.783 (for ds3 and e3 applications) specifically, if the user designs in the XRT75L03D along with a sonet/sdh mapper ic (which can be realized as either a standard product or as a custom logic solution, in an asic or fpga), then the followind can be accomplished; the mapper can receive an sts-n or an stm-m signal (which is carrying asynchronously-mapped ds3 and/ or e3 signals) and byte de-interleave this data into n sts-1 or 3*m vc-3 signals the mapper will then terminate these sts-1 or vc-3 signals and will de-map out this ds3 or e3 data from the incoming sts-1 spes or vc-3s, and output this ds3 or e3 to the ds3/e3 facility-side towards the XRT75L03D this ds3 or e3 signal (as it is output from these mapper devices) will contain a large amount intrinsic jitter and wander due to (1) the process of asynchronously mapping a ds3 or e3 signal into a sonet or sdh signal, (2) the occurrence of pointer adjustments within the sonet or sdh signal (transporting these ds3 or e3 signals) as it traverses the sonet/sdh network, and (3) clock gapping. when the XRT75L03D has been configured to operate in the "sonet/sdh de-sync" mode, then it will (1) accept this jittery ds3 or e3 clock and data signal from the mapper device (via the transmit system-side interface) and (2) through the jitter attenuator, the XRT75L03D will reduce the jitter and wander amplitude within these ds3 or e3 signals such that they (when output onto the line) will comply with the above- mentioned intrinsic jitter and wander specifications. 9.1 background and detailed information - sonet de-sync applications this section provides an in-depth discussion on the mechanisms that will cause jitter and wander within a ds3 or e3 signal that is being transported across a sonet or sdh network. a lot of this material is introductory, and can be skipped by the engineer that is already experienced in sonet/sdh designs. in this case, the user should proceed directly to section 9.8, designing with the XRT75L03D on page 118, which describes how to configure the XRT75L03D in the appropriate set of modes in order to support this application. in the wide-area network (wan) in north america it is often necessary to transport a ds3 signal over a long distance (perhaps over a thousand miles) in order to support a particular service. now rather than realizing this transport of ds3 data, by using over a thousand miles of coaxial cable (interspaced by a large number of ds3 repeaters) a common thing to do is to route this ds3 signal to a piece of equipment (such as a terminal mux, which in the "sonet community" is known as a pte or path terminating equipment). this terminal mux will asynchronously map the ds3 signal into a sonet signal. at this point, the sonet network will now transport this asynchronously mapped ds3 signal from one pte to another pte (which is located at the other end of the sonet network). once this sonet signal arrives at the remote pte, this ds3 signal will then be extracted from the sonet signal, and will be output to some other ds3 terminal equipment for further processing.
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 90 similar things are done outside of north america. in this case, this ds3 or e3 signal is routed to a pte, where it is asynchronously mapped into an sdh signal. this asynchronously mapped ds3 or e3 signal is then transported across the sdh network (from one pte to the pte at the other end of the sdh network). once this sdh signal arrives at the remote pte, this ds3 or e3 signal will then be extracted from the sdh signal, and will be output to some other ds3/e3 terminal equipment for further processing. figure 30 presents an illustration of this approach to transporting ds3 data over a sonet network as mentioned above a ds3 or e3 signal will be asynchronously mapped into a sonet or sdh signal and then transported over the sonet or sdh network. at the remote pte this ds3 or e3 signal will be extracted (or de-mapped) from this sonet or sdh signal, where it will then be routed to ds3 or e3 terminal equipment for further processing. in order to insure that this "de-mapped" ds3 or e3 signal can be routed to any industry-standard ds3 or e3 terminal equipment, without any complications or adverse effect on the network, the telcordia and itu-t standard committees have specified some limits on both the intrinsic jitter and wander that may exist within these ds3 or e3 signals as they are de-mapped from sonet/sdh. as a consequence, all ptes that maps and de-mapped ds3/e3 signals into/from sonet/sdh must be designed such that the ds3 or e3 data that is de-mapped from sonet/sdh by these ptes must meet these intrinsic jitter and wander requirements. as mentioned above, the XRT75L03D can assist the system designer (of sonet/sdh pte) by insuring that their design will meet these intrinsic jitter and wander requirements. this section of the data sheet will present the following information to the user. some background information on mapping ds3/e3 signals into sonet/sdh and de-mapping ds3/e3 signals from sonet/sdh. a brief discussion on the causes of jitter and wander within a ds3 or e3 signal that mapped into a sonet/ sdh signal, and is transported across the sonet/sdh network. a brief review of these intrinsic jitter and wander requirements in both sonet and sdh applications. a brief review on the intrinsic jitter and wander measurement results (of a de-mapped ds3 or e3 signal) whenever the XRT75L03D is used in a system design. f igure 30. a s imple i llustration of a ds3 signal being mapped into and transported over the sonet n etwork pte pte pte pte sonet network ds3 data ds3 data
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 91 a detailed discussion on how to design with and configure the XRT75L03D such that the end-system will meet these intrinsic jitter and wander requirements. in a sonet system, the relevant specification requirements for intrinsic jitter and wander (within a ds3 signal that is mapped into and then de-mapped from sonet) are listed below. telcordia gr-253-core category i intrinsic jitter requirements for ds3 applications (section 5.6), and ansi t1.105.03b-1997 - sonet jitter at network interfaces - ds3 wander supplement in general, there are three (3) sources of jitter and wander within an asynchronously-mapped ds3 signal that the system designer must be aware of. these sources are listed below. mapping/de-mapping jitter pointer adjustments clock gapping each of these sources of jitter/wander will be defined and discussed in considerable detail within this section. in order to accomplish all of this, this particular section will discuss all of the following topics in details. how ds3 data is mapped into sonet, and how this mapping operation contributes to jitter and wander within this "eventually de-mapped" ds3 signal. how this asynchronously-mapped ds3 data is transported throughout the sonet network, and how occurrences on the sonet network (such as pointer adjustments) will further contributes to jitter and wander within the "eventually de-mapped" ds3 signal. a review of the category i intrinsic jitter requirements (per telcordia gr-253-core) for ds3 applications a review of the ds3 wander requirements per ansi t1.105.03b-1997 a review of the intrinsic jitter and wander capabilities of the XRT75L03D in a typical system application an in-depth discussion on how to design with and configure the XRT75L03D to permit the system to the meet the above-mentioned intrinsic jitter and wander requirements n ote : an in-depth discussion on sdh de-sync applications will be presented in the next revision of this data sheet. 9.2 mapping/de-mapping jitter/wander mapping/de-mapping jitter (or wander) is defined as that intrinsic jitter (or wander) that is induced into a ds3 signal by the "asynchronous mapping" process. this section will discuss all of the following aspects of mapping/de-mapping jitter. how ds3 data is mapped into an sts-1 spe how frequency offsets within either the ds3 signal (being mapped into sonet) or within the sts-1 signal itself contributes to intrinsic jitter/wander within the ds3 signal (being transported via the sonet network). 9.2.1 how ds3 data is mapped into sonet whenever a ds3 signal is asynchronously mapped into sonet, this mapping is typically accomplished by a pte accepting ds3 data (from some remote terminal) and then loading this data into certain bit-fields within a given sts-1 spe (or synchronous payload envelope). at this point, this ds3 signal has now been asynchronously mapped into an sts-1 signal. in most applications, the sonet network will then take this particular sts-1 signal and will map it into "higher-speed" sonet signals (e.g., sts-3, sts-12, sts-48, etc.) and will then transport this asynchronously mapped ds3 signal across the sonet network, in this manner. as this "asynchronously-mapped" ds3 signal approaches its "destination" pte, this sts-1 signal will eventually be de-mapped from this sts-n signal. finally, once this sts-1 signal reaches the "destination" pte, then this asynchronously-mapped ds3 signal will be extracted from this sts-1 signal. 9.2.1.1 a brief description of an sts-1 frame in order to be able to describe how a ds3 signal is asynchronously mapped into an sts-1 spe, it is important to define and understand all of the following. the sts-1 frame structure
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 92 the sts-1 spe (synchronous payload envelope) telcordia gr-253-core's recommendation on mapping ds3 data into an sts-1 spe an sts-1 frame is a data-structure that consists of 810 bytes (or 6480 bits). a given sts-1 frame can be viewed as being a 9 row by 90 byte column array (making up the 810 bytes). the frame-repetition rate (for an sts-1 frame) is 8000 frames/second. therefore, the bit-rate for an sts-1 signal is (6480 bits/frame * 8000 frames/sec =) 51.84mbps. a simple illustration of this sonet sts-1 frame is presented below in figure 31. figure 31 indicates that the very first byte of a given sts-1 frame (to be transmitted or received) is located in the extreme upper left hand corner of the 90 column by 9 row array, and that the very last byte of a given sts- 1 frame is located in the extreme lower right-hand corner of the frame structure. whenever a network element transmits a sonet sts-1 frame, it starts by transmitting all of the data, residing within the top row of the sts- 1 frame structure (beginning with the left-most byte, and then transmitting the very next byte, to the right). after the network equipment has completed its transmission of the top or first row, it will then proceed to transmit the second row of data (again starting with the left-most byte, first). once the network equipment has transmitted the last byte of a given sts-1 frame, it will proceed to start transmitting the very next sts-1 frame. the illustration of the sts-1 frame (in figure 31) is very simplistic, for multiple reasons. one major reason is that the sts-1 frame consists of numerous types of bytes. for the sake of discussion within this data sheet, the sts-1 frame will be described as consisting of the following types (or groups) of bytes. the transport overheads (or toh) bytes the envelope capacity bytes 9.2.1.1.1 the transport overhead (toh) bytes the transport overhead or toh bytes occupy the very first three (3) byte columns within each sts-1 frame. figure 32 presents another simple illustration of an sts-1 frame structure. however, in this case, both the toh and the envelope capacity bytes are designated in this figure. f igure 31. a s imple i llustration of the sonet sts-1 f rame sts-1 frame (810 bytes) 90 bytes 9 rows first byte of the sts-1 frame last byte of the sts-1 frame
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 93 since the toh bytes occupy the first three byte columns of each sts-1 frame, and since each sts-1 frame consists of nine (9) rows, then we can state that the toh (within each sts-1 frame) consists of 3 byte columns x 9 rows = 27 bytes. the byte format of the toh is presented below in figure 33. f igure 32. a s imple i llustration of the sts-1 f rame s tructure with the toh and the e nvelope c apacity b ytes d esignated toh envelope capacity 87 bytes 3 bytes 90 bytes 9 row
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 94 in general, the role/purpose of the toh bytes is to fulfill the following functions. to support sts-1 frame synchronization to support error detection within the sts-1 frame to support the transmission of various alarm conditions such as rdi-l (line - remote defect indicator) and rei-l (line - remote error indicator) to support the transmission and reception of "section trace" messages to support the transmission and reception of oam&p messages via the dcc bytes (data communication channel bytes - d1 through d12 byte) the roles of most of the toh bytes is beyond the scope of this data sheet and will not be discussed any further. however, there are a three toh bytes that are important from the stand-point of this data sheet, and will discussed in considerable detail throughout this document. these are the h1 and h2 (e.g., the spe pointer) bytes and the h3 (e.g., the pointer action) byte. figure 34 presents an illustration of the byte-format of the toh within an sts-1 frame, with the h1, h2 and h3 bytes highlighted. f igure 33. t he b yte -f ormat of the toh within an sts-1 f rame a1 a1 b1 b1 d1 d1 h1 h1 b2 b2 d4 d4 s1 s1 d10 d10 d7 d7 c1 c1 f1 f1 d3 d3 h3 h3 k2 k2 d6 d6 e2 e2 d12 d12 d9 d9 a2 a2 e1 e1 d2 d2 h2 h2 k1 k1 d5 d5 m0 m0 d11 d11 d8 d8 envelope capacity bytes envelope capacity bytes 3 byte columns 87 byte columns 9 rows the toh bytes
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 95 although the role of the h1, h2 and h3 bytes will be discussed in much greater detail in section 9.3, jitter/ wander due to pointer adjustments on page 102. for now, we will simply state that the role of these bytes is two-fold. to permit a given pte (path terminating equipment) that is receiving an sts-1 data to be able to locate the sts-1 spe (synchronous payload envelope) within the envelope capacity of this incoming sts-1 data stream and, to inform a given pte whenever pointer adjustment and ndf (new data flag) events occur within the incoming sts-1 data-stream. 9.2.1.1.2 the envelope capacity bytes within an sts-1 frame in general, the envelope capacity bytes are any bytes (within an sts-1 frame) that exist outside of the toh bytes. in short, the envelope capacity contains the sts-1 spe (synchronous payload envelope). in fact, every single byte that exists within the envelope capacity also exists within the sts-1 spe. the only difference that exists between the "envelope capacity" as defined in figure 33 and figure 34 above and the sts-1 spe is that the envelope capacity is aligned with the sts-1 framing boundaries and the toh bytes; whereas the sts-1 spe is not aligned with the sts-1 framing boundaries, nor the toh bytes. the sts-1 spe is an "87 byte column x 9 row" data-structure (which is the exact same size as is the envelope capacity) that is permitted to "float" within the "envelope capacity". as a consequence, the sts-1 spe (within an sts-1 data-stream) will typically straddle across an sts-1 frame boundary. 9.2.1.1.3 the byte structure of the sts-1 spe as mentioned above, the sts-1 spe is an 87 byte column x 9 row structure. the very first column within the sts-1 spe consists of some overhead bytes which are known as the "path overhead" (or poh) bytes. the remaining portions of the sts-1 spe is available for "user" data. the byte structure of the sts-1 spe is presented below in figure 35. f igure 34. t he b yte -f ormat of the toh within an sts-1 f rame a1 a1 b1 b1 d1 d1 h1 h1 b2 b2 d4 d4 s1 s1 d10 d10 d7 d7 c1 c1 f1 f1 d3 d3 h3 h3 k2 k2 d6 d6 e2 e2 d12 d12 d9 d9 a2 a2 e1 e1 d2 d2 h2 h2 k1 k1 d5 d5 m0 m0 d11 d11 d8 d8 envelope capacity bytes envelope capacity bytes 3 byte columns 87 byte columns 9 rows the toh bytes
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 96 in general, the role/purpose of the poh bytes is to fulfill the following functions. to support error detection within the sts-1 spe to support the transmission of various alarm conditions such as rdi-p (path - remote defect indicator) and rei-p (path - remote error indicator) to support the transmission and reception of "path trace" messages the role of the poh bytes is beyond the scope of this data sheet and will not be discussed any further. 9.2.1.2 mapping ds3 data into an sts-1 spe now that we have defined the sts-1 spe, we can now describe how a ds3 signal is mapped into an sts-1 spe. as mentioned above, the sts-1 spe is basically an 87 byte column x 9 row structure of data. the very first byte column (e.g., in all 9 bytes) consists of the poh (path overhead) bytes. all of the remaining bytes within the sts-1 spe is simply referred to as "user" or "payload" data because this is the portion of the sts-1 signal that is used to transport "user data" from one end of the sonet network to the other. telcordia gr- 253-core specifies the approach that one must use to asynchronously map ds3 data into an sts-1 spe. in short, this approach is presented below in figure 36. f igure 35. i llustration of the b yte s tructure of the sts-1 spe z5 z5 z4 z4 z3 z3 h4 h4 f2 f2 g1 g1 c2 c2 b3 b3 j1 j1 payload (or user) data 86 bytes 1 byte 87 bytes 9 rows
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 97 figure 36 was copied directly out of telcordia gr-253-core. however, this figure can be simplified and redrawn as depicted below in figure 37. f igure 36. a n i llustration of t elcordia gr-253-core' s r ecommendation on how map ds3 data into an sts-1 spe f igure 37. a s implified "b it -o riented " v ersion of t elcordia gr-253-core' s r ecommendation on how to map ds3 data into an sts-1 spe ? for ds3 mapping, the sts-1 spe has the following structure. 25i i c3 r 25i i c2 r 25i c1 r r 25i i c3 r 25i i c2 r 25i c1 r r 25i i c3 r 25i i c2 r 25i c1 r r 25i i c3 r 25i i c2 r 25i c1 r r 25i i c3 r 25i i c2 r 25i c1 r r 25i i c3 r 25i i c2 r 25i c1 r r 25i i c3 r 25i i c2 r 25i c1 r r 25i i c3 r 25i i c2 r 25i c1 r r 25i i c3 r 25i i c2 r 25i c1 r r poh 87 bytes r = [r, r, r, r, r, r, r, r] i = [i, i, i, i, i, i, i, i] c1 = [r, r, c, i, i, i, i, i] c2 = [c, c, r, r, r, r, r, r] c3 = [c, c, r, r, o, o, r, s] i = ds3 data r = fixed stuff bit c = stuff control bit s = stuff opportunity bit o = overhead communications channel bit fixed stuff 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r 208i s 1r 2o 2r 2c 16r 208i 6r 2c 16r 205i c 18r r c s i o - fixed stuff bits - stuff control/indicator bits - ds3 data bits - stuff opportunity bits - overhead communication bits poh
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 98 figure 37 presents an alternative illustration of telcordia gr-253-core's recommendation on how to asynchronously map ds3 data into an sts-1 spe. in this case, the sts-1 spe bit-format is expressed purely in the form of "bit-types" and "numbers of bits within each of these types of bits". if one studies this figure closely he/she will notice that this is the same "87 byte column x 9 row" structure that we have been talking about when defining the sts-1 spe. however, in this figure, the "user-data" field is now defined and is said to consist of five (5) different types of bits. each of these bit-types play a role when asynchronously mapping a ds3 signal into an sts-1 spe. each of these types of bits are listed and described below. fixed stuff bits fixed stuff bits are simply "space-filler" bits that simply occupy space within the sts-1 spe. these bit-fields have no functional role other than "space occupation". telcordia gr-253-core does not define any particular value that these bits should be set to. each of the 9 rows, within the sts-1 spe will contain 59 of these "fixed stuff" bits. ds3 data bits the ds3 data-bits are (as its name implies) used to transport the ds3 data-bits within the sts-1 spe. if the sts-1 spe is transporting a framed ds3 data-stream, then these ds3 data bits will carry both the "ds3 payload data" and the "ds3 overhead bits". each of the 9 rows, within the sts-1 spe will contain 621 of these "ds3 data bits". this means that each sts-1 spe contains 5,589 of these ds3 data bit-fields. stuff opportunity bits the "stuff" opportunity bits will function as either a "stuff" (or junk) bit, or it will carry a ds3 data-bit. the decision as to whether to have a "stuff opportunity" bit transport a "ds3 data-bit" or a "stuff" bit depends upon the "timing differences" between the ds3 data that is being mapped into the sts-1 spe and the timing source that is driving the sts-1 circuitry within the pte. as will be described later on, these "stuff opportunity" bits play a very important role in "frequency-justifying" the ds3 data that is being mapped into the sts-1 spe. these "stuff opportunity" bits also play a critical role in inducing intrinsic jitter and wander within the ds3 signal (as it is de-mapped by the remote pte). each of the 9 rows, within the sts-1 spe consists of one (1) stuff opportunity bit. hence, there are a total of nine stuff opportunity" bits within each sts-1 spe. stuff control/indicator bits each of the nine (9) rows within the sts-1 spe contains five (5) stuff control/indicator bits. the purpose of these "stuff control/indicator" bits is to indicate (to the de-mapping pte) whether the "stuff opportunity" bits (that resides in the same row) is a "stuff" bit or is carrying a ds3 data bit. if all five of these "stuff control/indicator" bits, within a given row are set to "0", then this means that the corresponding "stuff opportunity" bit (e.g., the "stuff opportunity" bit within the same row) is carrying a ds3 data bit. conversely, if all five of these "stuff control/indicator" bits, within a given row are set to "1" then this means that the corresponding "stuff opportunity" bit is carrying a "stuff" bit. overhead communication bits telcordia gr-253-core permits the user to use these two bits (for each row) as some sort of "communications" bit. some mapper devices, such as the xrt94l43 12-channel ds3/e3/sts-1 to sts-12/ stm-1 mapper and the xrt94l33 3-channel ds3/e3/sts-1 to sts-3/stm-1 mapper ic (both from exar corporation) do permit the user to have access to these bit-fields. however, in general, these particular bits can also be thought of as "fixed stuff" bits, that mostly have a "space occupation" function. 9.2.2 ds3 frequency offsets and the use of the "stuff opportunity" bits in order to fully convey the role that the "stuff-opportunity" bits play, when mapping ds3 data into sonet, we will present a detailed discussion of each of the following "mapping ds3 into sts-1" scenarios. the ideal case (e.g., with no frequency offsets) the 44.736mbps + 1 ppm case
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 99 the 44.736mhz - 1ppm case throughout each of these cases, we will discuss how the resulting "bit-stuffing" (that was done when mapping the ds3 signal into sonet) affects the amount of intrinsic jitter and wander that will be present in the ds3 signal, once it is ultimately de-mapped from sonet. 9.2.2.1 the ideal case for mapping ds3 data into an sts-1 signal (e.g., with no frequency offsets) let us assume that we are mapping a ds3 signal, which has a bit rate of exactly 44.736mbps (with no frequency offset) into sonet. further, let us assume that the sonet circuitry within the pte is clocked at exactly 51.84mhz (also with no frequency offset), as depicted below. given the above-mentioned assumptions, we can state the following. the ds3 data-stream has a bit-rate of exactly 44.736mbps the pte will create 8000 sts-1 spe's per second in order to properly map a ds3 data-stream into an sts-1 data-stream, then each sts-1 spe must carry (44.736mbps/8000 =) 5592 ds3 data bits. is there a problem? according to figure 37, each sts-1 spe only contains 5589 bits that are specifically designated for "ds3 data bits". in this case, each sts-1 spe appears to be three bits "short". no there is a simple solution no, earlier we mentioned that each sts-1 spe consists of nine (9) "stuff opportunity" bits. therefore, these three additional bits (for ds3 data) are obtained by using three of these "stuff opportunity" bits. as a consequence, three (3) of these nine (9) "stuff opportunity" bits, within each sts-1 spe, will carry ds3 data- bits. the remaining six (6) "stuff opportunity" bits will typically function as "stuff" bits. in summary, for the "ideal case"; where there is no frequency offset between the ds3 and the sts-1 bit-rates, once this ds3 data-stream has been mapped into the sts-1 data-stream, then each and every sts-1 spe will have the following "stuff opportunity" bit utilization. 3 "stuff opportunity" bits will carry ds3 data bits. 6 "stuff opportunity" bits will function as "stuff" bits in this case, this ds3 signal (which has now been mapped into sts-1) will be transported across the sonet network. as this sts-1 signal arrives at the "destination pte", this pte will extract (or de-map) this ds3 data- stream from each incoming sts-1 spe. now since each and every sts-1 spe contains exactly 5592 ds3 data bits; then the bit rate of this ds3 signal will be exactly 44.736mbps (such as it was when it was mapped into sonet, at the "source" pte). f igure 38. a s imple i llustration of a ds3 d ata -s tream being m apped into an sts-1 spe, via a pte pte pte 44.736mhz + 0ppm ds3_data_in sts-1_data_out 51.84mhz + 0ppm
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 100 as a consequence, no "mapping/de-mapping" jitter or wander is induced in the "ideal case". 9.2.2.2 the 44.736mbps + 1ppm case the "above example" was a very ideal case. in reality, there are going to be frequency offsets in both the ds3 and sts-1 signals. for instance bellcore gr-499-core mandates that a ds3 signal have a bit rate of 44.736mbps 20ppm. hence, the bit-rate of a "bellcore" compliant ds3 signal can vary from the exact correct frequency for ds3 by as much of 20ppm in either direction. similarly, many sonet applications mandate that sonet equipment use at least a "stratum 3" level clock as its timing source. this requirement mandates that an sts-1 signal must have a bit rate that is in the range of 51.84 4.6ppm. to make matters worse, there are also provisions for sonet equipment to use (what is referred to as) a "sonet minimum clock" (smc) as its timing source. in this case, an sts-1 signal can have a bit-rate in the range of 51.84mbps 20ppm. in order to convey the impact that frequency offsets (in either the ds3 or sts-1 signal) will impose on the bit- stuffing behavior, and the resulting bit-rate, intrinsic jitter and wander within the ds3 signal that is being transported across the sonet network; let us assume that a ds3 signal, with a bit-rate of 44.736mbps + 1ppm is being mapped into an sts-1 signal with a bit-rate of 51.84mbps + 0ppm. in this case, the following things will occur. in general, most of the sts-1 spe's will each transport 5592 ds3 data bits. however, within a "one-second" period, a ds3 signal that has a bit-rate of 44.736mbps + 1 ppm will deliver approximately 44.7 additional bits (over and above that of a ds3 signal with a bit-rate of 44.736mbps + 0 ppm). this means that this particular signal will need to "negative-stuff" or map in an additional ds3 data bit every (1/44.736 =) 22.35ms. in other words, this additional ds3 data bit will need to be mapped into about one in every (22.35ms 8000 =) 178.8 sts-1 spes in order to avoid dropping any ds3 data-bits. what does this mean at the "source" pte? all of this means that as the "source" pte maps this ds3 signal, with a data rate of 44.736mbps + 1ppm into an sts-1 signal, most of the resulting "outbound" sts-1 spes will transport 5592 ds3 data bits (e.g., 3 stuff opportunity bits will be carrying ds3 data bits, the remaining 6 stuff opportunity bits are "stuff" bits, as in the "ideal" case). however, in approximately one out of 178.8 "outbound" sts-1 spes, there will be a need to insert an additional ds3 data bit within this sts-1 spe. whenever this occurs, then (for these particular sts- 1 spes) the spe will be carrying 5593 ds3 data bits (e.g., 4 stuff opportunity bits will be carrying ds3 data bits, the remaining 5 stuff opportunity bits are "stuff" bits). figure 39 presents an illustration of the sts-1 spe traffic that will be generated by the "source" pte, during this condition. f igure 39. a n i llustration of the sts-1 spe traffic that will be generated by the "s ource " pte, when mapping in a ds3 signal that has a bit rate of 44.736m bps + 1 ppm , into an sts-1 signal source pte source pte 44.736mbps + 1ppm 5592 ds3 data bits 5592 ds3 data bits 5592 ds3 data bits 5592 ds3 data bits spe # n spe # n+1 5592 ds3 data bits 5592 ds3 data bits spe # n+177 5593 ds3 data bits 5593 ds3 data bits 5592 ds3 data bits 5592 ds3 data bits spe # n+178 spe # n+179 extra ds3 data bit stuffed here sts-1 spe data stream
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 101 what does this mean at the "destination" pte? in this case, this ds3 signal (which has now been mapped into an sts-1 data-stream) will be transported across the sonet network. as this sts-1 signal arrives at the "destination" pte, this pte will extract (or de- map) this ds3 data from each incoming sts-1 spe. now, in this case most (e.g., 177/178.8) of the incoming sts-1 spes will contain 5592 ds3 data-bits. therefore, the nominal data rate of the ds3 signal being de- mapped from sonet will be 44.736mbps. however, in approximately 1 out of every 178 incoming sts-1 spes, the spe will carry 5593 ds3 data-bits. this means that (during these times) the data rate of the de- mapped ds3 signal will have an instantaneous frequency that is greater than 44.736mbps. these "excursion" of the de-mapped ds3 data-rate, from the nominal ds3 frequency can be viewed as occurrences of "mapping/ de-mapping" jitter. since each of these "bit-stuffing" events involve the insertion of one ds3 data bit, we can say that the amplitude of this "mapping/de-mapping" jitter is approximately 1ui-pp. from this point on, we will be referring to this type of jitter (e.g., that which is induced by the mapping and de-mapping process) as "de- mapping" jitter. since this occurrence of "de-mapping" jitter is periodic and occurs once every 22.35ms, we can state that this jitter has a frequency of 44.7hz. 9.2.2.3 the 44.736mbps - 1ppm case in this case, let us assume that a ds3 signal, with a bit-rate of 44.736mbps - 1ppm is being mapped into an sts-1 signal with a bit-rate of 51.84mbps + 0ppm. in this case, the following this will occur. in general, most of the sts-1 spes will each transport 5592 ds3 data bits. however, within a "one-second" period a ds3 signal that has a bit-rate of 44.736mbps - 1ppm will deliver approximately 45 too few bits below that of a ds3 signal with a bit-rate of 44.736mbps + 0ppm. this means that this particular signal will need to "positive-stuff" or exclude a ds3 data bit from mapping every (1/44.736) = 22.35ms. in other words, we will need to avoid mapping this ds3 data-bit about one in every (22.35ms*8000) = 178.8 sts-1 spes. what does this mean at the "source" pte? all of this means that as the "source" pte maps this ds3 signal, with a data rate of 44.736mbps - 1ppm into an sts-1 signal, most of the resulting "outbound" sts-1 spes will transport 5592 ds3 data bits (e.g., 3 stuff opportunity bits will be carrying ds3 data bits, the remaining 6 stuff opportunity bits are "stuff" bits). however, in approximately one out of 178.8 "outbound" sts-1 spes, there will be a need for a "positive-stuffing" event. whenever these "positive-stuffing" events occur then (for these particular sts-1 spes) the spe will carry only 5591 ds3 data bits (e.g., in this case, only 2 stuff opportunity bits will be carrying ds3 data-bits, and the remaining 7 stuff opportunity bits are "stuff" bits). figure 40 presents an illustration of the sts-1 spe traffic that will be generated by the "source" pte, during this condition.
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 102 what does this mean at the destination pte? in this case, this ds3 signal (which has now been mapped into an sts-1 data-stream) will be transported across the sonet network. as this sts-1 signal arrives at the "destination" pte, this pte will extract (or de- map) this ds3 data from each incoming sts-1 spe. now, in this case, most (e.g., 177/178.8) of the incoming sts-1 spes will contain 5592 ds3 data-bits. therefore, the nominal data rate of the ds3 signal being de- mapped from sonet will be 44.736mbps. however, in approximately 1 out of every 178 incoming sts-1 spes, the spe will carry only 5591 ds3 data bits. this means that (during these times) the data rate of the de- mapped ds3 signal will have an instantaneous frequency that is less than 44.736mbps. these "excursions" of the de-mapped ds3 data-rate, from the nominal ds3 frequency can be viewed as occurrences of mapping/de- mapping jitter with an amplitude of approximately 1ui-pp. since this occurrence of "de-mapping" jitter is periodic and occurs once every 22.35ms, we can state that this jitter has a frequency of 44.7hz. we talked about de-mapping jitter, what about de-mapping wander? the telcordia and bellcore specifications define "wander" as "jitter with a frequency of less than 10hz". based upon this definition, the ds3 signal (that is being transported by sonet) will cease to contain jitter and will now contain "wander", whenever the frequency offset of the ds3 signal being mapped into sonet is less than 0.2ppm. 9.3 jitter/wander due to pointer adjustments in the previous section, we described how a ds3 signal is asynchronously-mapped into sonet, and we also defined "mapping/de-mapping" jitter. in this section, we will describe how occurrences within the sonet network will induce jitter/wander within the ds3 signal that is being transported across the sonet network. in order to accomplish this, we will discuss the following topics in detail. the concept of an sts-1 spe pointer the concept of pointer adjustments the causes of pointer adjustments how pointer adjustments induce jitter/wander within a ds3 signal being transported by that sonet network. 9.3.1 the concept of an sts-1 spe pointer as mentioned earlier, the sts-1 spe is not aligned to the sts-1 frame boundaries and is permitted to "float" within the envelope capacity. as a consequence, the sts-1 spe will often times "straddle" across two f igure 40. a n i llustration of the sts-1 spe traffic that will be generated by the s ource pte, when mapping a ds3 signal that has a bit rate of 44.736m bps - 1 ppm , into an sts-1 signal source pte source pte 44.736mbps - 1ppm 5592 ds3 data bits 5592 ds3 data bits 5592 ds3 data bits 5592 ds3 data bits spe # n spe # n+1 5592 ds3 data bits 5592 ds3 data bits spe # n+177 5591 ds3 data bits 5591 ds3 data bits 5592 ds3 data bits 5592 ds3 data bits spe # n+178 spe # n+179 ds3 data bit excluded here sts-1 spe data stream
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 103 consecutive sts-1 frames. figure 41 presents an illustration of an sts-1 spe straddling across two consecutive sts-1 frames. a pte that is receiving and terminating an sts-1 data-stream will perform the following tasks. it will acquire and maintain sts-1 frame synchronization with the incoming sts-1 data-stream. once the pte has acquired sts-1 frame synchronization, then it will locate the j1 byte (e.g., the very byte within the very next sts-1 spe) within the envelope capacity by reading out the contents of the h1 and h2 bytes. the h1 and h2 bytes are referred to (in the sonet standards) as the spe pointer bytes. when these two bytes are concatenated together in order to form a 16-bit word (with the h1 byte functioning as the "most significant byte") then the contents of the "lower" 10 bit-fields (within this 16-bit word) reflects the location of the j1 byte within the envelope capacity of the incoming sts-1 data-stream. figure 42 presents an illustration of the bit format of the h1 and h2 bytes, and indicates which bit-fields are used to reflect the location of the j1 byte. f igure 41. a n i llustration of an sts-1 spe straddling across two consecutive sts-1 frames toh sts-1 frame n sts-1 frame n + 1 j1 byte (1 st byte of spe) j1 byte (1 st byte of next spe) h1, h2 bytes spe can straddle across two sts-1 frames
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 104 figure 43 relates the contents within these 10 bits (within the h1 and h2 bytes) to the location of the j1 byte (e.g., the very first byte of the sts-1 spe) within the envelope capacity. n otes : 1. if the content of the "pointer bits" is "0x00" then the j1 byte is located immediately after the h3 byte, within the envelope capacity. 2. if the contents of the 10-bit expression exceed the value of 0x30f (or 782, in decimal format) then it does not contain a valid pointer value. 9.3.2 pointer adjustments within the sonet network the word sonet stands for "synchronous optical network. this name implies that the entire sonet network is synchronized to a single clock source. however, because the sonet (and sdh) networks can f igure 42. t he b it - format of the 16-b it w ord ( consisting of the h1 and h2 bytes ) with the 10 bits , reflecting the location of the j1 byte , designated f igure 43. t he r elationship between the c ontents of the "p ointer b its " ( e . g ., the 10- bit expression within the h1 and h2 bytes ) and the l ocation of the j1 b yte within the e nvelope c apacity of an sts- 1 f rame x x x x x x x x x x s s n n n n lsb msb h2 byte h1 byte 10 bit pointer expression 521 520 * * * * * * * * * * 436 435 e2 m0 s1 434 433 * * * * * * * * * * 349 348 d12 d11 d10 347 346 * * * * * * * * * * 262 261 d9 d8 d7 260 259 * * * * * * * * * * 175 174 d6 d5 d4 173 172 * * * * * * * * * * 88 87 k2 k1 b2 86 85 * * * * * * * * * * 1 0 h3 h2 h1 782 781 * * * * * * * * * * 697 696 d3 d2 d1 695 694 * * * * * * * * * * 610 609 f1 e1 b1 608 607 * * * * * * * * * * 523 522 c1/j0 a2 a1 toh the pointer value 0 is immediately after the h3 byte
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 105 span thousands of miles, traverse many different pieces of equipments, and even cross international boundaries; in practice, the sonet/sdh network is not synchronized to a single clock source. in practice, the sonet/sdh network can be thought of as being divided into numerous "synchronization islands". each of these "synchronization islands" will consist of numerous pieces of sonet terminal equipment. each of these pieces of sonet terminal equipment will all be synchronized to a single stratum-1 clock source which is the most accurate clock source within the synchronization island. typically a "synchronization island" will consist of a single "timing master" equipment along with multiple "timing slave" pieces of equipment. this "timing master" equipment will be directly connected to the stratum-1 clock source and will have the responsibility of distributing a very accurate clock signal (that has been derived from the stratum 1 clock source) to each of the "timing slave" pieces of equipment within the "synchronization island". the purpose of this is to permit each of the "timing slave" pieces of equipment to be "synchronized" with the "timing master" equipment, as well as the stratum 1 clock source. typically this "clock distribution" is performed in the form of a bits (building integrated timing supply) clock, in which a very precise clock signal is provided to the other pieces of equipment via a t1 or e1 line signal. many of these "synchronization islands" will use a stratum-1" clock source that is derived from gps pulses that are received from satellites that operate at geo-synchronous orbit. other "synchronization islands" will use a stratum-1" clock source that is derived from a very precise local atomic clock. as a consequence, different "synchronization islands" will use different stratum 1 clock sources. the up-shot of having these "synchronization islands" that use different "stratum-1 clock" sources, is that the stratum 1 clock frequencies, between these "synchronization islands" are likely to be slightly different from each other. these "frequency- differences" within stratum 1 clock sources will result in "clock-domain changes" as a sonet signal (that is traversing the sonet network) passes from one "synchronization island" to another. the following section will describe how these "frequency differences" will cause a phenomenon called "pointer adjustments" to occur in the sonet network. 9.3.3 causes of pointer adjustments the best way to discuss how pointer adjustment events occur is to consider an sts-1 signal, which is driven by a timing reference of frequency f1; and that this sts-1 signal is being routed to a network equipment (that resides within a different "synchronization island") and processes sts-1 data at a frequency of f2. n ote : clearly, both frequencies f1 and f2 are at the sts-1 rate (e.g., 51.84mhz). however, these two frequencies are likely to be slightly different from each other. now, since the sts-1 signal (which is of frequency f1) is being routed to the network element (which is operating at frequency f2), the typical design approach for handling "clock-domain" differences is to route this sts-1 signal through a "slip buffer" as illustrated below.
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 106 in the "slip buffer, the "input" sts-1 data (labeled "sts-1 data_in") is latched into the fifo, upon a given edge of the corresponding "sts-1 clock_f1" input clock signal. the sts-1 data (labeled "sts-1 data_out") is clocked out of the slip buffer upon a given edge of the "sts-1 clock_f2" input clock signal. the behavior of the data, passing through the "slip buffer" is now described for each possible relationship between frequencies f1 and f2. if f1 = f2 if both frequencies, f1 and f2 are exactly equal, then the sts-1 data will be "clocked" into the "slip buffer" at exactly the same rate that it is "clocked out". in this case, the "slip buffer" will neither fill-up nor become depleted. as a consequence, no pointer-adjustments will occur in this sts-1 data stream. in other words, the sts-1 spe will remain at a constant location (or offset) within each sts-1 envelope capacity for the duration that this sts-1 signal is supporting this particular service. if f1 < f2 if frequency f1 is less than f2, then this means that the sts-1 data is being "clocked out" of the "slip buffer" at a faster rate than it is being clocked in. in this case, the "slip buffer" will eventually become depleted. whenever this occurs, a typical strategy is to "stuff" (or insert) a "dummy byte" into the data stream. the purpose of stuffing this "dummy byte" is to compensate for the frequency differences between f1 and f2, and attempt to keep the "slip buffer, at a somewhat constant fill level. n ote : this "dummy byte" does not carry any valuable information (not for the user, nor for the system). since this "dummy byte" carries no useful information, it is important that the "receiving pte" be notified anytime this "dummy byte" stuffing occurs. this way, the receiving terminal can "know" not to treat this "dummy byte" as user data. byte-stuffing and pointer incrementing in a sonet network whenever this "byte-stuffing" occurs then the following other things occur within the sts-1 data stream. during the sts-1 frame that contains the "byte-stuffing" event a. the "stuff-byte" will be inserted into the byte position immediately after the h3 byte. this insertion of the "dummy byte" immediately after the h3 byte position will cause the j1 byte (and in-turn, the rest of the spe) to be "byte-shifted" away from the h3 byte. as a consequence, the offset between the h3 byte posi- tion and the sts-1 spe will now have been increased by 1 byte. b. the "transmitting" network equipment will notify the remote terminal of this byte-stuffing event, by invert- ing certain bits within the "pointer word" (within the h1 and h2 bytes) that are referred to as "i" bits. f igure 44. a n i llustration of an sts-1 signal being processed via a s lip b uffer slip buffer slip buffer sts-1 data_in sts-1 clock_f1 sts-1 data_out sts-1 clock_f2 clock domain operating at frequency f1 clock domain operating at frequency f2.
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 107 figure 45 presents an illustration of the bit-format within the 16-bit word (consist of the h1 and h2 bytes) with the "i" bits designated. n ote : at this time the "i" bits are inverted in order to denote that an "incrementing" pointer adjustment event is currently occurring. during the sts-1 frame that follows the "byte-stuffing" event the "i" bits (within the "pointer-word") will be set back to their normal value; and the contents of the h1 and h2 bytes will be incremented by "1". if f1 > f2 if frequency f1 is greater than f2, then this means that the sts-1 data is being clocked into the "slip buffer" at a faster rate than is being clocked out. in this case, the "slip buffer" will start to fill up. whenever this occurs, a typical strategy is to delete (e.g., negative-stuff) a byte from the slip buffer. the purpose of this "negative- stuffing" is to compensate for the frequency differences between f1 and f2; and to attempt to keep the "slip buffer" at a somewhat constant fill-level. n ote : this byte, which is being "un-stuffed" does carry valuable information for the user (e.g., this byte is typically a payload byte). therefore, whenever this negative stuffing occurs, two things must happen. a. the "negative-stuffed" byte must not be simply discarded. in other words, it must somehow also be transmitted to the remote pte with the remainder of the spe data. b. the remote pte must be notified of the occurrence of these "negative-stuffing" events. further, the remote pte must know where to obtain this "negative-stuffed" byte. negative-stuffing and pointer-decrementing in a sonet network whenever this "byte negative-stuffing" occurs then the following other things occur within the sts-1 data- stream. during the sts-1 frame that contains the "negative byte-stuffing" event a. the "negative-stuffed" byte will be inserted into the h3 byte position. whenever an spe data byte is inserted into the h3 byte position (which is ordinarily an unused byte), the number of bytes that will exist between the h3 byte and the j1 byte within the very next spe will be reduced by 1 byte. as a consequence, in this case, the j1 byte (and in-turn, the rest of the spe) will now be "byte-shifted" towards the h3 byte position. b. the "transmitting" network element will notify the remote terminal of this "negative-stuff" event by inverting certain bits within the "pointer word" (within the h1 and h2 bytes) that are referred to as "d" bits. f igure 45. a n i llustration of the b it f ormat within the 16- bit word ( consisting of the h1 and h2 bytes ) with the "i" bits designated d i d i d i d i d i s s n n n n lsb msb h2 byte h1 byte 10 bit pointer expression
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 108 figure 46 presents an illustration of the bit format within the 16-bit word (consisting of the h1 and h2 bytes) with the "d" bits designated. n ote : at this time the "d" bits are inverted in order to denote that a "decrementing" pointer adjustment event is currently occurring. during the sts-1 frame that follows the "negative byte-stuffing" event the "d" bits (within the pointer-word) will be set back to their normal value; and the contents of the h1 and h2 bytes will be decremented by one. f igure 46. a n i llustration of the b it -f ormat within the 16- bit word ( consisting of the h1 and h2 bytes ) with the "d" bits designated d i d i d i d i d i s s n n n n lsb msb h2 byte h1 byte 10 bit pointer expression
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 109 9.3.4 why are we talking about pointer adjustments? the overall sonet network consists of numerous "synchronization islands". as a consequence, whenever a sonet signal is being transmitted from one "synchronization island" to another; that sonet signal will undergo a "clock domain" change as it traverses the network. this clock domain change will result in periodic pointer-adjustments occurring within this sonet signal. depending upon the direction of this "clock-domain" shift that the sonet signal experiences, there will either be periodic "incrementing" pointer-adjustment events or periodic "decrementing" pointer-adjustment events within this sonet signal. regardless of whether a given sonet signal is experiencing incrementing or decrementing pointer adjustment events, each pointer adjustment event will result in an abrupt 8-bit shift in the position of the spe within the sts-1 data-stream. if this sts-1 signal is transporting an "asynchronously-mapped" ds3 signal; then this 8-bit shift in the location of the spe (within the sts-1 signal) will result in approximately 8uipp of jitter within the asynchronously-mapped ds3 signal, as it is de-mapped from sonet. in section 9.5, a review of the category i intrinsic jitter requirements (per telcordia gr-253-core) for ds3 applications on page 110 we will discuss the "category i intrinsic jitter requirements (for ds3 applications) per telcordia gr-253- core. however, for now we will simply state that this 8uipp of intrinsic jitter far exceeds these "intrinsic jitter" requirements. in summary, pointer-adjustments events are a "fact of life" within the sonet/sdh network. further, pointer- adjustment events, within a sonet signal that is transporting an asynchronously-mapped ds3 signal, will impose a significant impact on the intrinsic jitter and wander within that ds3 signal as it is de-mapped from sonet. 9.4 clock gapping jitter in most applications (in which the XRT75L03D will be used in a sonet de-sync application) the user will typically interface the XRT75L03D to a mapper device in the manner as presented below in figure 47. in this application, the mapper ic will have the responsibility of receiving an sts-n signal (from the sonet network) and performing all of the following operations on this sts-n signal. byte-de-interleaving this incoming sts-n signal into n sts-1 signals terminating each of these sts-1 signals extracting (or de-mapping) the ds3 signal(s) from the spes within each of these terminated sts-1 signals. f igure 47. i llustration of the t ypical a pplications for the XRT75L03D in a sonet d e -s ync a pplica - tion ds3 to sts-n mapper/ demapper ic ds3 to sts-n mapper/ demapper ic XRT75L03D XRT75L03D sts-n signal tpdata_n input pin tclk_n input de-mapped (gapped) ds3 data and clock
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 110 in this application, these mapper devices can be thought of as multi-channel devices. for example, an sts-3 mapper can be viewed as a 3-channel ds3/sts-1 to sts-3 mapper ic. similarly, an sts-12 mapper can be viewed as a 12-channel ds3/sts-1 to sts-12 mapper ic. continuing on with this line of thought, if a mapper ic is configured to receive an sts-n signal, and (from this sts-n signal) de-map and output n ds3 signals (towards the ds3 facility), then it will typically do so in the following manner. in many cases, the mapper ic will output this ds3 signal, using both a "data-signal" and a "clock-signal". in many cases, the mapper ic will output the contents of an entire sts-1 data-stream via the data-signal. however, as the mapper ic output this sts-1 data-stream, it will typically supply clock pulses (via the clock- signal output) coincident to whenever a ds3 bit is being output via the data-signal. in this case, the mapper ic will not supply a clock pulse coincident to when a toh, poh, or any "non-ds3 data-bit" is being output via the "data-signal". now, since the mapper ic will output the entire sts-1 data stream (via the data-signal), the output clock- signal will be of the form such that it has a period of 19.3ns (e.g., a 51.84mhz clock signal). however, the mapper ic will still generate approximately 44,736,000 clock pulses during any given one second period. hence, the clock signal that is output from the mapper ic will be a horribly gapped 44.736mhz clock signal. one can view such a clock signal as being a very-jittery 44.736mhz clock signal. this jitter that exists within the "clock-signal" is referred to as "clock-gapping" jitter. a more detailed discussion on how the user must handle this type of jitter is presented in section 9.8.2, recommendations on pre-processing the gapped clocks (from the mapper/asic device) prior to routing this ds3 clock and data-signals to the transmit inputs of the XRT75L03D on page 121. 9.5 a review of the category i intrinsic jitter requirements (per telcordia gr-253-core) for ds3 applications the "category i intrinsic jitter requirements" per telcordia gr-253-core (for ds3 applications) mandates that the user perform a large series of tests against certain specified "scenarios". these "scenarios" and their corresponding requirements is summarized in table 31, below. t able 31: s ummary of "c ategory i i ntrinsic j itter r equirement per t elcordia gr-253-core, for ds3 applications s cenario d escription s cenario n umber t elcordia gr-253-core c ategory i i ntrinsic j itter r equirements c omments ds3 de-mapping jitter 0.4ui-pp includes effects of de-mapping and clock gapping jitter single pointer adjustment a1 0.3ui-pp + ao includes effects of jitter from clock-gapping, de-map- ping and pointer adjustments.note: ao is the amount of intrinsic jitter that was measured during the "ds3 de- mapping jitter" phase of the test. pointer bursts a2 1.3ui-pp includes effects of jitter from clock-gapping, de-map- ping and pointer adjustments. phase transients a3 1.2ui-pp includes effects of jitter from clock-gapping, de-map- ping and pointer adjustments. 87-3 pattern a4 1.0ui-pp includes effects of jitter from clock-gapping, de-map- ping and pointer adjustments. 87-3 add a5 1.3ui-pp includes effects of jitter from clock-gapping, de-map- ping and pointer adjustments. 87-3 cancel a5 1.3ui-pp includes effects of jitter from clock-gapping, de-map- ping and pointer adjustments.
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 111 n ote : all of these intrinsic jitter measurements are to be performed using a band-pass filter of 10hz to 400khz. each of the scenarios presented in table 31, are briefly described below. 9.5.1 ds3 de-mapping jitter ds3 de-mapping jitter is the amount of intrinsic jitter that will be measured within the "line" or "facility-side" ds3 signal, (after it has been de-mapped from a sonet signal) without the occurrence of "pointer adjustments" within the sonet signal. telcordia gr-253-core requires that the "ds3 de-mapping" jitter be less than 0.4ui-pp, when measured over all possible combinations of ds3 and sts-1 frequency offsets. 9.5.2 single pointer adjustment telcordia gr-253-core states that if each pointer adjustment (within a continuous stream of pointer adjustments) is separated from each other by a period of 30 seconds, or more; then they are sufficiently isolated to be considered "single-pointer adjustments". figure 48 presents an illustration of the "single pointer adjustment" scenario. telcordia gr-253-core states that the intrinsic jitter that is measured (within the ds3 signal) that is ultimately de-mapped from a sonet signal that is experiencing "single-pointer adjustment" events, must not exceed the value 0.3ui-pp + ao. n otes : 1. ao is the amount of intrinsic jitter that was measured during the "de-mapping" jitter portion of this test. 2. testing must be performed for both incrementing and decrementing pointer adjustments. continuous pattern a4 1.0ui-pp includes effects of jitter from clock-gapping, de-map- ping and pointer adjustments. continuous add a5 1.3ui-pp includes effects of jitter from clock-gapping, de-map- ping and pointer adjustments. continuous cancel a5 1.3ui-pp includes effects of jitter from clock-gapping, de-map- ping and pointer adjustments. f igure 48. i llustration of s ingle p ointer a djustment s cenario t able 31: s ummary of "c ategory i i ntrinsic j itter r equirement per t elcordia gr-253-core, for ds3 applications s cenario d escription s cenario n umber t elcordia gr-253-core c ategory i i ntrinsic j itter r equirements c omments initialization cool down measurement period > 30s pointer adjustment events
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 112 9.5.3 pointer burst figure 49 presents an illustration of the "pointer burst" pointer adjustment scenario per telcordia gr-253- core. telcordia gr-253-core mandates that the intrinsic jitter, within the ds3 signal that is de-mapped from a sonet signal, which is experiencing the "burst of pointer adjustment" scenario, must not exceed 1.3ui-pp. 9.5.4 phase transients figure 50 presents an illustration of the "phase transients" pointer adjustment scenario per telcordia gr-253- core. f igure 49. i llustration of b urst of p ointer a djustment s cenario f igure 50. i llustration of "p hase -t ransient " p ointer a djustment s cenario initialization cool down measurement period > 30s pointer adjustment events 0.5ms t pointer adjustment burst train 0.5ms initialization cool down measurement period > 30s pointer adjustment events 0.25s t pointer adjustment burst train 0.25s 0.5s
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 113 telcordia gr-253-core mandates that the intrinsic jitter, within the ds3 signal that is de-mapped from a sonet signal, which is experiencing the "phase transient - pointer adjustment" scenario must not exceed 1.2ui-pp. 9.5.5 87-3 pattern figure 51 presents an illustration of the "87-3 continuous pattern" pointer adjustment scenario per telcordia gr-253-core. telcordia gr-253-core defines an "87-3 continuous" pointer adjustment pattern, as a repeating sequence of 90 pointer adjustment events. within this 90 pointer adjustment event, 87 pointer adjustments are actually executed. the remaining 3 pointer adjustments are never executed. the spacing between individual pointer adjustment events (within this scenario) can range from 7.5ms to 10seconds. telcordia gr-253-core mandates that the intrinsic jitter, within the ds3 signal that is de-mapped from a sonet signal, which is experiencing the "87-3 continuous" pattern of pointer adjustments, must not exceed 1.0ui-pp. 9.5.6 87-3 add figure 52 presents an illustration of the "87-3 add pattern" pointer adjustment scenario per telcordia gr-253- core. f igure 51. a n i llustration of the 87-3 c ontinuous p ointer a djustment p attern initialization measurement period repeating 87-3 pattern (see below) pointer adjustment events 87-3 pattern 87 pointer adjustment events no pointer adjustments t note: t ranges from 34ms to 10s (req) t ranges from 7.5ms to 34ms (obj)
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 114 telcordia gr-253-core defines an "87-3 add" pointer adjustment, as the "87-3 continuous" pointer adjustment pattern, with an additional pointer adjustment inserted, as shown above in figure 52. telcordia gr-253-core mandates that the intrinsic jitter, within the ds3 signal that is de-mapped from a sonet signal, which is experiencing the "87-3 add" pattern of pointer adjustments, must not exceed 1.3ui-pp. 9.5.7 87-3 cancel figure 53 presents an illustration of the 87-3 cancel pattern pointer adjustment scenario per telcordia gr- 253-core. f igure 52. i llustration of the 87-3 a dd p ointer a djustment p attern f igure 53. i llustration of 87-3 c ancel p ointer a djustment s cenario 43 pointer adjustments 43 pointer adjustments added pointer adjustment no pointer adjustments tt 86 or 87 pointer adjustments no pointer adjustments t cancelled pointer adjustment
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 115 telcordia gr-253-core defines an "87-3 cancel" pointer adjustment, as the "87-3 continuous" pointer adjustment pattern, with an additional pointer adjustment cancelled (or not executed), as shown above in figure 53. telcordia gr-253-core mandates that the intrinsic jitter, within the ds3 signal that is de-mapped from a sonet signal, which is experiencing the "87-3 cancel" pattern of pointer adjustments, must not exceed 1.3ui- pp. 9.5.8 continuous pattern figure 54 presents an illustration of the "continuous" pointer adjustment scenario per telcordia gr-253- core. telcordia gr-253-core mandates that the intrinsic jitter, within the ds3 signal that is de-mapped from a sonet signal, which is experiencing the "continuous" pattern of pointer adjustments, must not exceed 1.0ui- pp. the spacing between individual pointer adjustments (within this scenario) can range from 7.5ms to 10s. 9.5.9 continuous add figure 55 presents an illustration of the "continuous add pattern" pointer adjustment scenario per telcordia gr-253-core. f igure 54. i llustration of c ontinuous p eriodic p ointer a djustment s cenario initialization measurement period repeating continuous pattern (see below) pointer adjustment events t
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 116 telcordia gr-253-core defines an "continuous add" pointer adjustment, as the "continuous" pointer adjustment pattern, with an additional pointer adjustment inserted, as shown above in figure 55. telcordia gr-253-core mandates that the intrinsic jitter, within the ds3 signal that is de-mapped from a sonet signal, which is experiencing the "continuous add" pattern of pointer adjustments, must not exceed 1.3ui-pp. 9.5.10 continuous cancel figure 56 presents an illustration of the "continuous cancel pattern" pointer adjustment scenario per telcordia gr-253-core. f igure 55. i llustration of c ontinuous -a dd p ointer a djustment s cenario f igure 56. i llustration of c ontinuous -c ancel p ointer a djustment s cenario continuous pointer adjustments continuous pointer adjustments added pointer adjustment tt continuous pointer adjustments t cancelled pointer adjustment
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 117 telcordia gr-253-core defines a "continuous cancel" pointer adjustment, as the "continuous" pointer adjustment pattern, with an additional pointer adjustment cancelled (or not executed), as shown above in figure 56. telcordia gr-253-core mandates that the intrinsic jitter, within the ds3 signal that is de-mapped from a sonet signal, which is experiencing the "continuous cancel" pattern of pointer adjustments, must not exceed 1.3ui-pp. 9.6 a review of the ds3 wander requirements per ansi t1.105.03b-1997. to be provided in the next revision of this data sheet. 9.7 a review of the intrinsic jitter and wander capabilities of the XRT75L03D in a typical system application the intrinsic jitter and wander test results are summarized in this section. 9.7.1 intrinsic jitter test results the intrinsic jitter test results for the XRT75L03D in ds3 being de-mapped from sonet is summarized below in table 2. n otes : 1. a detailed test report on our test procedures and test results is available and can be obtained by contacting your exar sales representative. 2. these test results were obtained via the xrt75l03s mounted on our xrt94l43 12-channel ds3/e3/sts-1 mapper evaluation board. 3. these same results apply to sdh/au-3 mapping applications. t able 32: s ummary of "c ategory i i ntrinsic j itter t est r esults " for sonet/ds3 a pplications s cenario d escription s cenario n umber XRT75L03D i ntrinsic j itter t est r esults t elcordia gr-253-core c ategory i i ntrinsic j itter r equirements ds3 de-mapping jitter 0.13ui-pp 0.4ui-pp single pointer adjustment a1 0.201ui-pp 0.43ui-pp (e.g. 0.13ui-pp + 0.3ui-pp) pointer bursts a2 0.582ui-pp 1.3ui-pp phase transients a3 0.526ui-pp 1.2ui-pp 87-3 pattern a4 0.790ui-pp 1.0ui-pp 87-3 add a5 0.926ui-pp 1.3ui-pp 87-3 cancel a5 0.885ui-pp 1.3ui-pp continuous pattern a4 0.497ui-pp 1.0ui-pp continuous add a5 0.598ui-pp 1.3ui-pp continuous cancel a5 0.589ui-pp 1.3ui-pp
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 118 9.7.2 wander measurement test results wander measurement test results will be provided in the next revision of the XRT75L03D data sheet. 9.8 designing with the XRT75L03D in this section, we will discuss the following topics. how to design with and configure the XRT75L03D to permit a system to meet the above-mentioned intrinsic jitter and wander requirements. how is the XRT75L03D able to meet the above-mentioned requirements? how does the XRT75L03D permits the user to comply with the sonet aps recovery time requirements of 50ms (per telcordia gr-253-core)? how should one configure the XRT75L03D, if one needs to support "daisy-chain" testing at the end customer's site? 9.8.1 how to design and configure the XRT75L03D to permit a system to meet the above- mentioned intrinsic jitter and wander requirements as mentioned earlier, in most application (in which the XRT75L03D will be used in a sonet de-sync application) the user will typically interface the XRT75L03D to a mapper device in the manner as presented below in figure 57. in this application, the mapper has the responsibility of receiving a sonet sts-n/oc-n signal and extracting as many as n ds3 signals from this signal. as a given channel within the mapper ic extracts out a given ds3 signal (from sonet) it will typically be applying a clock and data signal to the "transmit input" of the liu ic. figure 57 presents a simple illustration as to how one channel, within the XRT75L03D should be connected to the mapper ic. as mentioned above, the mapper ic will typically output a clock and data signal to the XRT75L03D. in many cases, the mapper ic will output the contents of an entire sts-1 data-stream via the data signal to the XRT75L03D. however, the mapper ic typically only supplies a clock pulse via the clock signal to the XRT75L03D coincident to whenever a ds3 bit is being output via the data signal. in this case, the mapper ic would not supply a clock edge coincident to when a toh, poh or any non-ds3 data-bit is being output via the data-signal. f igure 57. i llustration of the XRT75L03D being connected to a m apper ic for sonet d e -s ync a ppli - cations ds3 to sts-n mapper/ demapper ic ds3 to sts-n mapper/ demapper ic XRT75L03D XRT75L03D sts-n signal tpdata_n input pin tclk_n input de-mapped (gapped) ds3 data and clock
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 119 figure 57 indicates that the data signal from the mapper device should be connected to the tpdata_n input pin of the liu ic and that the clock signal from the mapper device should be connected to the tclk_n input pin of the liu ic. in this application, the XRT75L03D has the following responsibilities. using a particular clock edge within the "gapped" clock signal (from the mapper ic) to sample and latch the value of each ds3 data-bit that is output from the mapper ic. to (through the user of the jitter attenuator block) attenuate the jitter within this "ds3 data" and "clock signal" that is output from the mapper ic. to convert this "smoothed" ds3 data and clock into industry-compliant ds3 pulses, and to output these pulses onto the line. to configure the XRT75L03D to operate in the correct mode for this application, the user must execute the following configuration steps. a. configure the XRT75L03D to operate in the ds3 mode the user can configure a given channel (within the XRT75L03D) to operate in the ds3 mode, by executing either of the following steps. if the XRT75L03D has been configured to operate in the host mode the user can accomplish this by setting both bits 2 (e3_n) and bits 1 (sts-1/ds3*_n), within each of the "channel control registers" to "0" as depicted below. if the XRT75L03D has been configured to operate in the hardware mode the user can accomplish this by pulling all of the following input pins "low". pin 76 - e3_0 pin 94 - e3_1 pin 85 - e3_2 pin 72 - sts-1/ds3 _0 pin 98 - sts-1/ds3 _1 pin 81 - sts-1/ds3 _2 b. configure the XRT75L03D to operate in the single-rail mode since the mapper ic will typically output a single "data line" and a "clock line" for each ds3 signal that it demaps from the incoming sts-n signal, it is imperative to configure each channel within the XRT75L03D to operate in the single rail mode. the user can accomplish this by executing either of the following steps. if the XRT75L03D has been configured to operate in the host mode the user can accomplish this by setting bit 0 (sr/dr*), within the each of the "channel control" registers to 1, as illustrated below. channel control register - channel 0 address location = 0x06 channel 1 address location = 0x0e channel 2 address location = 0x16 b it 7b it 6b it 5b it 4b it 3b it 2b it 1 b it 0 unused prbs enable ch_n rlb_n llb_n e3_n sts-1/ds3 _n sr/dr _n r/o r/o r/w r/w r/w r/w r/w r/w 0000000 0
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 120 if the XRT75L03D has been configured to operate in the hardware mode then the user should tie pin 65 (sr/dr*) to "high". c. configure each of the three channels within the XRT75L03D to operate in the sonet de-sync mode the user can accomplish this by executing either of the following steps. if the XRT75L03D has been configured to operate in the host mode. then the user should set bit d2 (ja0) to "0" and bit d0 (ja1) to "1", within the jitter attenuator control register, as depicted below. if the XRT75L03D has been configured to operate in the hardware mode then the user should tie pin 44 (ja0) to a logic "high" and pin 42 (ja1) to a logic "low". once the user accomplishes either of these steps, then the jitter attenuator (within the XRT75L03D) will be configured to operate with a very narrow bandwidth. d. configure the jitter attenuator (within each of three three channels) to operate in the transmit direction. the user can accomplish this by executing either the following steps. if the XRT75L03D has been configured to operate in the host mode. then the user should be bit d1 (jatx/jarx*) to "1", within the jitter attenuator control register, as depicted below. channel control register - channel 0 address location = 0x06 channel 1 address location = 0x0e channel 2 address location = 0x16 b it 7b it 6b it 5b it 4b it 3b it 2b it 1 b it 0 unused prbs enable ch_n rlb_n llb_n e3_n sts-1/ ds3 _n sr/dr _n r/o r/o r/w r/w r/w r/w r/w r/w 0000000 1 jitter attenuator control register - (channel 0 address location = 0x07 channel 1 address location = 0x0f channel 2 address location = 0x17 b it 7b it 6b it 5b it 4b it 3 b it 2b it 1 b it 0 unused sonet aps recovery time disablech_n ja reset ch_n ja1 ch_n ja in tx path ch_n ja0 ch_n r/o r/o r/o r/w r/w r/w r/w r/w 00000 00 1
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 121 if the XRT75L03D has been configured to operate in the hardware mode. then the user should tie pin 43 (jatx/jarx*) to "1". e. enable the "sonet aps recovery time" mode finally, if the user intends to use the XRT75L03D in an application that is required to reacquire proper sonet and ds3 traffic, prior within 50ms of an aps (automatic protection switching) event (per telcordia gr-253- core), then the user should set bit 4 (sonet aps recovery time disable), within the "jitter attenuator control" register, to "0" as depicted below. n otes : 1. the ability to disable the "sonet aps recovery time" mode is only available if the XRT75L03D is operating in the host mode. if the XRT75L03D is operating in the "hardware" mode, then this "sonet aps recovery time mode" feature will always be enabled. 2. the "sonet aps recovery time" mode will be discussed in greater detail in section 9.8.3, how does the XRT75L03D permit the user to comply with the sonet aps recovery time requirements of 50ms (per telcordia gr-253-core)? on page 126. 9.8.2 recommendations on pre-processing the gapped clocks (from the mapper/asic device) prior to routing this ds3 clock and data-signals to the transmit inputs of the XRT75L03D in order to minimize the effects of "clock-gapping" jitter within the ds3 signal that is ultimately transmitted to the ds3 line (or facility), we recommend that some "pre-processing" of the "data-signals" and "clock-signals" (which are output from the mapper device) be implemented prior to routing these signals to the "transmit inputs" of the XRT75L03D. jitter attenuator control register - channel 0 address location = 0x07 channel 1 address location = 0x0f channel 2 address location = 0x17 b it 7b it 6b it 5b it 4b it 3b it 2 b it 1b it 0 unused sonet aps recovery time disablech_n ja reset ch_n ja1 ch_n ja in tx path ch_n ja0 ch_n r/o r/o r/o r/w r/w r/w r/w r/w 000000 11 jitter attenuator control register - channel 0 address location = 0x07 channel 1 address location = 0x0f channel 2 address location = 0x17 b it 7b it 6b it 5 b it 4b it 3b it 2b it 1b it 0 unused sonet aps recovery time disablech_n ja reset ch_n ja1 ch_n ja in tx path ch_n ja0 ch_n r/o r/o r/o r/wr/wr/wr/wr/w 000 00001
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 122 9.8.2.1 some notes prior to starting this discussion: our simulation results indicate that jitter attenuator pll (within the XRT75L03D liu ic) will have no problem handling and processing the "data-signal" and "clock-signal" from a mapper ic/asic if no pre-processing has been performed on these signals. in order words, our simulation results indicate that the jitter attenuator pll (within the liu ic) will have no problem handling the "worst-case" of 59 consecutive bits of no clock pulses in the "clock-signal (due to the mapper ic processing the toh bytes, an incrementing pointer-adjustment- induced "stuffed-byte", the poh byte, and the two fixed-stuff bytes within the sts-1 spe, etc), immediately followed be processing clusters of ds3 data-bits (as shown in figure 37) and still comply with the "category i intrinsic jitter requirements per telcordia gr-253-core for ds3 applications. n ote : if this sort of "pre-processing" is already supported by the mapper device that you are using, then no further action is required by the user. 9.8.2.2 our pre-processing recommendations for the time-being, we recommend that the customer implement the "pre-processing" of the ds3 "data-signal" and "clock-signal" as described below. currently we are aware that some of the mapper products on the market do implement this exact "pre-processing" algorithm. however, if the customer is implementing their mapper design in an asic or fpga solution, then we strongly recommend that the user implement the necessary logic design to realize the following recommendations. some time ago, we spent some time, studying (and then later testing our solution with) the pm5342 oc-3 to ds3 mapper ic from pmc-sierra. in particular, we wanted to understand the type of "ds3 clock" and "data" signal that this ds3 to oc-3 mapper ic outputs. during this effort, we learned the following. 1. this "ds3 clock" and "data" signal, which is output from the mapper ic consists of two major "repeating" patterns (which we will refer to as "major pattern a" and "major pattern b". the behavior of each of these patterns is presented below. major pattern a major pattern a consists of two "sub" or minor-patterns, (which we will refer to as "minor pattern p1 and p2). minor pattern p1 consists of a string of seven (7) clock pulses, followed by a single gap (no clock pulse). an illustration of minor pattern p1 is presented below in figure 58. it should be noted that each of these clock pulses has a period of approximately 19.3ns (or has an "instantaneously frequency of 51.84mhz). minor pattern p2 consists of string of five (5) clock pulses, which is also followed by a single gap (no clock pulse). an illustration of pattern p2 is presented below in figure 59. f igure 58. i llustration of minor pattern p1 1 2 3 4 5 6 7 missing clock pulse
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 123 how major pattern a is synthesized major pattern a is created (by the mapper ic) by: repeating minor pattern p1 (e.g., 7 clock pulses, followed by a gap) 63 times. upon completion of the 63rd transmission of minor pattern p1, minor pattern p2 is transmitted repeatedly 36 times. figure 60 presents an illustration which depicts the procedure that is used to synthesize major pattern a hence, major pattern a consists of "(63 x 7) + (36 x 5)" = 621 clock pulses. these 621 clock pulses were delivered over a period of "(63 x 8) + (36 x 6)" = 720 sts-1 (or 51.84mhz) clock periods. major pattern b major pattern b consists of three sub or minor-patterns (which we will refer to as "minor patterns p1, p2 and p3). minor pattern p1, which is used to partially synthesize major pattern b, is exactly the same "minor pattern p1" as was presented above in figure 30. similarly, the minor pattern p2, which is also used to partially synthesize major pattern b, is exactly the same "minor pattern p2" as was presented in figure 31. minor pattern p3 (which has yet to be defined) consists of a string of six (6) clock pulses, which contains no gaps. an illustration of minor pattern p3 is presented below in figure 61. f igure 59. i llustration of minor pattern p2 f igure 60. i llustration of p rocedure which is used to s ynthesize major pattern a 1 2 3 4 5 missing clock pulse minor pattern p1 minor pattern p2 repeats 63 times repeats 36 times
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 124 how major pattern b is synthesized major pattern b is created (by the mapper ic) by: repeating minor pattern p1 (e.g., 7 clock pulses, followed by a gap) 63 times. upon completion of the 63rd transmission of minor pattern p1, minor pattern p2 is transmitted repeatedly 36 times. pon completion of the 35th transmission of minor pattern p2, minor pattern p3 is transmitted once. figure 62 presents an illustration which depicts the procedure that is used to synthesize major pattern b. hence, major pattern b consists of "(63 x 7) + (35 x 5)" + 6 = 622 clock pulses. these 622 clock pulses were delivered over a period of "(63 x 8) + (35 x 6) + 6 = 720 sts-1 (or 51.84mhz) clock periods. putting the patterns together finally, the ds3 to oc-n mapper ic clock output is reproduced by doing the following. major pattern a is transmitted two times (repeatedly). after the second transmission of major pattern a, major pattern b is transmitted once. then the whole process repeats. throughout the remainder of this document, we will refer to this particular pattern as the "super pattern". figure 63 presents an illustration of this "super pattern" which is output via the mapper ic. f igure 61. i llustration of minor pattern p3 f igure 62. i llustration of p rocedure which is used to s ynthesize pattern b 1 2 3 4 5 6 pattern p1 pattern p2 repeats 63 times repeats 35 times pattern p3 transmitted 1 time
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 125 cross-checking our data each super pattern consists of (621 + 621 + 622) = 1864 clock pulses. the total amount of time, which is required for the "ds3 to oc-n mapper" ic to transmit this super pattern is (720 + 720 + 720) = 2160 "sts-1" clock periods. this amount to a period of (2160/51.84mhz) = 41,667ns. in a period of 41, 667ns, the XRT75L03D (when configured to operate in the ds3 mode), will output a total (41,667ns x 44,736,000) = 1864 uniformly spaced ds3 clock pulses. hence, the number of clock pulses match. applying the super pattern to the XRT75L03D whenever the XRT75L03D is configured to operate in a "sonet de-sync" application, the device will accept a continuous string of the above-defined super pattern, via the tclk input pin (along with the corresponding data). the channel within the XRT75L03D (which will be configured to operate in the "ds3" mode) will output a ds3 line signal (to the ds3 facility) that complies with the "category i intrinsic jitter requirements - per telcordia gr-253-core (for ds3 applications). this scheme is illustrated below in figure 64. according to this figure, the jitter attenuator will receive a very jitter ds3 or e3 signal (e.g., data and clock signals) from the mapper device via the "transmit system-side" input pins of the liu ic. f igure 63. i llustration of the super pattern which is output via the "oc-n to ds3" m apper ic f igure 64. s imple i llustration of the XRT75L03D being used in a sonet d e -s ynchronizer " a pplica - tion pattern a pattern a pattern b ds3 to sts-n mapper/ demapper ic ds3 to sts-n mapper/ demapper ic XRT75L03D XRT75L03D sts-n signal tpdata_n input pin tclk_n input de-mapped (gapped) ds3 data and clock
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 126 9.8.3 how does the XRT75L03D permit the user to comply with the sonet aps recovery time requirements of 50ms (per telcordia gr-253-core)? telcordia gr-253-core, section 5.3.3.3 mandates that the "aps completion" (or recovery) time be 50ms or less. many of our customers interpret this particular requirement as follows. "from the instant that an aps is initiated on a high-speed sonet signal, all lower-speed sonet traffic (which is being transported via this "high-speed" sonet signal) must be fully restored within 50ms. similarly, if the "high-speed" sonet signal is transporting some pdh signals (such as ds1 or ds3, etc.), then those entities that are responsible for acquiring and maintaining ds1 or ds3 frame synchronization (with these ds1 or ds3 data-streams that have been de-mapped from sonet) must have re-acquired ds1 or ds3 frame synchronization within 50ms" after aps has been initiated." the XRT75L03D was designed such that the ds3 signals that it receives from a sonet mapper device and processes will comply with the category i intrinsic jitter requirements per telcordia gr-253-core. reference 1 documents some aps recovery time testing, which was performed to verify that the jitter attenuator blocks (within the XRT75L03D) device that permit it to comply with the category i intrinsic jitter requirements (for ds3 applications) per telcordia gr-253-core, do not cause it to fail to comply with the "aps completion time" requirements per section 5.3.3.3 of telcordia gr-253-core. however, table 3 presents a summary of some aps recovery time requirements that were documented within this test report. ta b l e 3 , n ote : the aps completion (or recovery) time requirement is 50ms. configuring the XRT75L03D to be able to comply with the sonet aps recovery time requirements of 50ms quite simply, the user can configure a given jitter attenuator block (associated with a given channel) to (1) comply with the "aps completion time" requirements per telcordia gr-253-core, and (2) also comply with the "category i intrinsic jitter requirements per telcordia gr-253-core (for ds3 applications) by making sure that bit 4 (sonet aps recovery time disable ch_n), within the jitter attenuator control register is set to "0" as depicted below. t able 33: m easured aps r ecovery t ime as a function of ds3 ppm offset ds3 ppm o ffset ( per w&g ant-20se) m easured aps r ecovery t ime ( per l ogic a nalyzer ) -99 ppm 1.25ms -40ppm 1.54ms -30 ppm 1.34ms -20 ppm 1.49ms -10 ppm 1.30ms 0 ppm 1.89ms +10 ppm 1.21ms +20 ppm 1.64ms +30 ppm 1.32ms +40 ppm 1.25ms +99 ppm 1.35ms
XRT75L03D ? ? ? ? rev. 1.0.0 three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer 127 n ote : the user can only disable the "sonet aps recovery time mode" if the XRT75L03D is operating in the host mode. if the user is operating the XRT75L03D in the hardware mode, then the user will have no ability to disable the "sonet aps recovery time mode" feature. 9.8.4 how should one configure the XRT75L03D, if one needs to support "daisy-chain" testing at the end customer's site? daisy-chain testing is emerging as a new requirements that many of our customers are imposing on our sonet mapper and liu products. many system designer/manufacturers are finding out that whenever their end-customers that are evaluating and testing out their systems (in order to determine if they wish to move forward and start purchasing this equipment in volume) are routinely demanding that they be able to test out these systems with a single piece of test equipment. this means that the end-customer would like to take a single piece of ds3 or sts-1 test equipment and (with this test equipment) snake the ds3 or sts-1 traffic (that this test equipment will generate) through many or (preferably all) channels within the system. for example, we have had request from our customers that (on a system that supports oc-192) our silicon be able to support this ds3 or sts-1 traffic snaking through the 192 ds3 or sts-1 ports within this system. after extensive testing, we have determined that the best approach to complying with test "daisy-chain" testing requirements, is to configure the jitter attenuator blocks (within each of the channels within the XRT75L03D) into the "32-bit" mode. the user can configure the jitter attenuator block (within a given channel of the XRT75L03D) to operate in this mode by settings in the table below. references 1. test report - automatic protection switching (aps) recovery time testing with the xrt94l43 ds3/e3/sts-1 to sts-12 mapper ic - revision c silicon jitter attenuator control register - channel 0 address location = 0x07 channel 1 address location = 0x0f channel 2 address location = 0x17 b it 7b it 6b it 5 b it 4b it 3b it 2b it 1b it 0 unused sonet aps recovery time disable ch_n ja reset ch_n ja1 ch_n ja in tx path ch_n ja0 ch_n r/o r/o r/o r/wr/wr/wr/wr/w 000 00011 jitter attenuator control register - channel 0 address location = 0x07 channel 1 address location = 0x0f channel 2 address location = 0x17 b it 7b it 6b it 5b it 4b it 3 b it 2b it 1 b it 0 unused sonet aps recovery time disable ch_n ja reset ch_n ja1 ch_n ja in tx path ch_n ja0 ch_n r/o r/o r/o r/w r/w r/w r/w r/w 00000 11 0
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 128 ordering information p art n umber p ackage o perating t emperature r ange XRT75L03Div 14 x 20 mm 128 pin lqfp - 40 c to + 85 c package dimensions - 14x20 mm, 128 pin package e b 1 38 39 64 65 102 103 128 a 2 a a 1 a a a a l c e1 d d1 n ote: the control dim ensions are the m illim eter colum n the heat slug is at the center of the package. min max 0.055 max min 0.874 0.008 0.011 0.057 0.006 1.60 1.40 0.063 0.783 0.858 0.004 0.007 0.053 0.002 0.27 1.45 19.90 21.80 0.09 0.17 1.35 0.15 0.05 0.791 0.030 0.555 0.638 0.018 0.020 bsc 0.547 0.622 20.10 22.20 0.20 0.50 bsc 14.10 13.90 16.20 15.80 0.75 millimeters 0.45 0 o 7 o 0 o 7 o symbol d1 d c b a2 a1 a inches l e e1 e a copper heat slug solder plated exposed on package bottom b b 0.370 0.390 9.40 9.90
? ? ? ? XRT75L03D three channel e3/ds3/sts-1 line interface unit with sonet desynchronizer rev. 1.0.0 129 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2003 exar corporation datasheet june 2003. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revisions r evision d ate c omments 1.0.0 june 2003 initial issue

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